{"schema_version":1,"experiment_id":"eoa_inverse_innovation_exp12_substrate_denial72_20260805","research_id":"eoa_inverse_innovation_exp12_light_screen_20260805","cell_id":"activation_decay_measurement__computer_science","search_lanes":{"direct_problem_and_intervention":{"queries":["DRAM refresh sentinel cells replica cells retention time adaptive refresh charge leakage","DRAM canary cells refresh retention monitor adaptive refresh"],"source_ids":["SRC1","SRC2"],"no_result_note":null},"synonyms_and_historical_terms":{"queries":["patent DRAM dummy cell leakage monitor refresh timing retention reference cell","patent DRAM reference cell retention time refresh adaptive dummy capacitor","DRAM replica bitline replica cell self refresh retention time sensor"],"source_ids":["SRC1","SRC2"],"no_result_note":null},"products_practices_and_standards":{"queries":["JEDEC DRAM refresh temperature compensated self refresh retention standard","site:micron.com DDR4 SDRAM datasheet refresh 64ms self refresh temperature controlled PDF"],"source_ids":["SRC3","SRC4"],"no_result_note":null},"component_combination":{"queries":["DRAM monitor cell remaining charge voltage comparators refresh pulse per bank","retention time monitor DRAM refresh circuit replica cell","Replica Technique for Adaptive Refresh Timing gain-cell embedded DRAM"],"source_ids":["SRC1","SRC2","SRC4"],"no_result_note":null}},"sources":[{"source_id":"SRC1","title":"US6483764B2 — Dynamic DRAM refresh rate adjustment based on cell leakage monitoring","publisher":"IBM; Google Patents","url":"https://patents.google.com/patent/US6483764B2/en","source_type":"OTHER","claims_supported":["A 2001-priority disclosure directly measures leakage in an integrated DRAM monitor cell and adjusts refresh rate from the measurement.","The monitor cell is charged and evaluated through separate gates, with its remaining voltage applied to multiple differential comparators against critical signal-margin levels.","The disclosure permits separate monitor and refresh circuitry for each DRAM bank and recharges the monitor after evaluation.","It identifies temperature, process variation, voltage fluctuation, and noise as contributors that make temperature alone an incomplete leakage proxy."]},{"source_id":"SRC2","title":"Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM","publisher":"IEEE Transactions on Circuits and Systems II; author-hosted via ResearchGate","url":"https://www.researchgate.net/publication/261719196_Replica_Technique_for_Adaptive_Refresh_Timing_of_Gain-Cell-Embedded_DRAM","source_type":"PRIMARY_RESEARCH","claims_supported":["A fabricated 2-kb gain-cell eDRAM used an integrated replica-cell column to track retention across process, voltage, temperature, and access-statistics variation.","Replica cells were periodically read and calibrated to fail before the worst array cell, thereby controlling adaptive refresh timing.","Silicon measurements reported retention tracking across supply voltages and activity conditions and more than fivefold lower refresh frequency than worst-case timing."]},{"source_id":"SRC3","title":"Micron Technology FAQs — DRAM refresh and timing guidance","publisher":"Micron Technology","url":"https://www.micron.com/sales-support/sales/faqs","source_type":"OFFICIAL_GUIDANCE","claims_supported":["Micron states that DRAM timing must continue to satisfy the refresh interval even in reduced-speed operating modes.","Micron explains that reading or writing every row within the refresh time can substitute for explicit refresh and gives 8,192 rows per 64 ms as an example.","The guidance cautions that operation outside documented device limits is unsupported and can cause malfunction or timing violations."]},{"source_id":"SRC4","title":"RAIDR: Retention-Aware Intelligent DRAM Refresh","publisher":"ACM/IEEE International Symposium on Computer Architecture; ETH Zurich host","url":"https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf","source_type":"PRIMARY_RESEARCH","claims_supported":["Commodity DRAM commonly uses a 64-ms cell refresh interval, with 7.8-microsecond average auto-refresh commands below 85 degrees Celsius and a doubled command rate at higher temperature.","Refresh blocks memory service, consumes energy, and is unnecessarily frequent for most cells because retention times vary.","Retention-aware refresh is established adjacent research, including row profiling, retention bins, temperature scaling, and conservative maximum-rate fallback when tracking structures cannot ensure correctness."]}],"problem_evidence":{"status":"SUPPORTED","finding":"The underlying problem is clearly visible: stored capacitor charge leaks with time and context, insufficient refresh risks invalid data, and conservative uniform refresh consumes energy and blocks availability. Retention variation and imperfect temperature-only proxies are also documented.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"closest_prior_art":[{"name":"IBM dynamic DRAM refresh-rate adjustment based on cell-leakage monitoring","source_ids":["SRC1"],"overlap":"Substantially reproduces the proposed core: an integrated, chargeable DRAM monitor cell; direct remaining-charge measurement; multiple voltage comparators tied to sense margin; local or per-bank circuitry; measurement-driven refresh adjustment; and monitor recharge after evaluation.","remaining_difference":"The proposal more specifically uses several isolated 1T1C sentinels destructively sampled at staggered fixed delays, treats their ordered crossings as a decay profile, and mandates explicit measurement-fault fallback. Those details were not found together in SRC1."},{"name":"Replica technique for adaptive refresh timing of gain-cell eDRAM","source_ids":["SRC2"],"overlap":"Uses physically integrated, deliberately conservative replica cells that track local retention and operating conditions, are periodically sensed, and govern adaptive refresh; it was demonstrated in fabricated silicon.","remaining_difference":"It concerns 2T gain-cell eDRAM and a periodically read replica column rather than the proposal's parallel staggered 1T1C probes, analog decay-curve taps, and explicit conservative oscillator fallback."},{"name":"RAIDR retention-aware intelligent refresh","source_ids":["SRC4"],"overlap":"Adapts refresh by local retention requirements, recognizes refresh energy and availability costs, incorporates temperature variation, and uses conservative behavior when correctness cannot be assured.","remaining_difference":"RAIDR relies on characterized row-retention bins and controller metadata rather than direct analog sensing of sacrificial-cell charge followed by a hardwired threshold-triggered pulse."}],"prior_art_disposition":"SUBSTANTIAL_COLLISION","contrastive_claim_remaining":"A narrow testable distinction remains: within conventional 1T1C DRAM, several physically matched but refresh-isolated sentinels are destructively sampled at staggered hardware delays, their ordered analog threshold crossings provide a local decay-shape check rather than one leakage sample, and inconsistent or missing crossings directly force a conservative refresh oscillator. The broader matched-monitor-cell, comparator, local adaptive-refresh mechanism is already disclosed.","contrastive_claim_falsifier":"The distinction is falsified by a pre-existing disclosure or implementation combining refresh-isolated local 1T1C replica cells, multiple staggered destructive probes, ordered comparator crossings used to govern refresh, and automatic conservative fallback; experimentally, it is also falsified if multiple taps do not bound protected cells more reliably than the closest single-monitor or replica-column designs across process, voltage, temperature, access-pattern, and aging variation.","gates":{"adequate_source_search":{"status":"PASS","rationale":"The bounded search covered direct language, sentinel/canary/replica/dummy and leakage-monitor terminology, manufacturer and standards-related practices, retention-aware research, patents, comparators, per-bank monitoring, and refresh-pulse combinations. Four opened sources span four publication contexts and include primary research and first-party guidance.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"supported_problem":{"status":"PASS","rationale":"All four sources make the leakage-driven integrity requirement visible, while primary research also documents refresh energy and availability overhead and heterogeneous retention.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"distinct_testable_claim":{"status":"PASS","rationale":"Although the broad mechanism substantially collides with prior art, the precise combination of staggered destructive probes, ordered decay-segment validation, and fault-forced fallback remains separately stated and falsifiable.","source_ids":["SRC1","SRC2"]},"bounded_next_test":{"status":"PASS","rationale":"The proposed isolated coupon, finite cell counts, predefined temperature/supply/load points, earliest-data-cell comparison, injected sensor/comparator faults, and unchanged production settings form a bounded mechanism test. Prior fabricated-array work supports testing across voltage and activity, while retention-profiling research warns that pattern and variable-retention effects must be included before broader inference.","source_ids":["SRC2","SRC4"]},"no_obvious_safety_or_authority_stop":{"status":"PASS","rationale":"No obvious stop applies to a nonproduction coupon with a conservative oscillator, injected-fault checks, explicit halt conditions, and no reduction of production refresh settings. Any production or irreplaceable-data use would require substantially broader validation because the sentinel may not represent the weakest cell.","source_ids":["SRC1","SRC2","SRC3","SRC4"]}},"screen_survival":false,"world_novelty_boundary":"This bounded public-web screen found substantial collision with prior monitor-cell and replica-cell adaptive-refresh mechanisms. It cannot establish world novelty, patentability, freedom to operate, market size, expert acceptance, production safety, or realized value."}