{"schema_version":1,"experiment_id":"eoa_inverse_innovation_exp12_substrate_denial72_20260805","research_id":"eoa_inverse_innovation_exp12_light_screen_20260805","cell_id":"authority_mentor_relationship_anchoring__computer_science","search_lanes":{"direct_problem_and_intervention":{"queries":["analog memristor crossbar reference array differential error current programming conductance matching","physical reference-coupled training analog computing array error current programming","patent analog array clone reference array output current programming memristor"],"source_ids":["SRC1","SRC2","SRC3"],"no_result_note":null},"synonyms_and_historical_terms":{"queries":["memristor crossbar closed loop write verify device variation analog conductance array","in situ training memristor crossbar error current weight update hardware array variation","reference resistor array memristor programming tuning"],"source_ids":["SRC1","SRC2","SRC3"],"no_result_note":null},"products_practices_and_standards":{"queries":["analog in-memory computing chip conductance variability calibration programming official","memristor crossbar iterative programming write verify","programming memristor arrays high precision analog computing"],"source_ids":["SRC3","SRC4"],"no_result_note":null},"component_combination":{"queries":["differential current comparator programming pulses memristor crossbar teacher array","twin analog arrays simultaneous voltage probe mismatch current adaptive programming","analog circuit calibration replica reference circuit adaptive trimming error current"],"source_ids":["SRC2","SRC3","SRC4"],"no_result_note":"No retained source disclosed the full combination of two characterized computing arrays, simultaneous multi-line transfer-response comparison, purely analog mismatch-driven programming, staged physical decoupling, standalone retention, and a secondary-reference cross-check."}},"sources":[{"source_id":"SRC1","title":"Signal and noise extraction from analog memory elements for neuromorphic computing","publisher":"Nature Communications (Springer Nature)","url":"https://www.nature.com/articles/s41467-018-04485-1","source_type":"PRIMARY_RESEARCH","claims_supported":["Experiments on 1000 phase-change-memory devices fabricated by an identical process separated device-to-device variability from inherent update randomness.","Analog ReRAM and PCM conductance updates are nonlinear, stochastic, and device-dependent.","Conductance-encoded crossbars perform vector-matrix multiplication through applied voltages and sensed column currents."]},{"source_id":"SRC2","title":"US8416604B2: Method of implementing memristor-based multilevel memory using reference resistor array","publisher":"United States Patent and Trademark Office, accessed via Google Patents","url":"https://patents.google.com/patent/US8416604B2/en","source_type":"OTHER","claims_supported":["Prior art applies identical probe currents to a reference resistor array and a selected memristor, differentially compares their voltages, and applies polarity-correct programming pulses until the mismatch falls below a threshold.","The disclosed pulse width can be proportional to mismatch magnitude, and the programmed state remains in the memristor after writing.","Its target is a selected scalar resistance level from a passive reference ladder, not a peer computing array's realized multi-input, multi-output transfer behavior."]},{"source_id":"SRC3","title":"Gradient descent-based programming of analog in-memory computing cores","publisher":"IEEE International Electron Devices Meeting; manuscript hosted by arXiv/Zenodo","url":"https://arxiv.org/abs/2305.16647","source_type":"PRIMARY_RESEARCH","claims_supported":["Whole-core programming can minimize measured matrix-vector-multiplication error rather than independently matching every unit-cell conductance.","The method experimentally improved inference accuracy on two phase-change-memory analog in-memory-computing cores.","The reported optimization uses digitally computed gradient descent and an externally represented target matrix, unlike a direct analog bridge between peer arrays."]},{"source_id":"SRC4","title":"Programming memristor arrays with arbitrarily high precision for analog computing","publisher":"Science (American Association for the Advancement of Science)","url":"https://www.science.org/doi/10.1126/science.adi9405","source_type":"PRIMARY_RESEARCH","claims_supported":["Reading noise and writing variability limit scalable, accurate memristor analog computing.","A demonstrated system compensates earlier devices' programming errors with subsequently programmed devices to improve aggregate computing precision.","The demonstrated solution uses multiple devices, digital peripheral precision, and a prescribed computation target rather than transferring the realized response of a removable peer reference array."]}],"problem_evidence":{"status":"PARTLY_SUPPORTED","finding":"The physical transmission gap is credible and visible: nominally similar analog-memory devices exhibit device-to-device variability, stochastic and nonlinear pulse response, while core-level work treats MVM programming error as a material accuracy problem. The retained evidence does not directly measure two nominally identical complete arrays programmed from the same table over the proposal's declared multi-line probe surface, so that exact whole-array formulation remains to be demonstrated.","source_ids":["SRC1","SRC3","SRC4"]},"closest_prior_art":[{"name":"Reference-resistor-array closed-loop memristor programming (US8416604B2)","source_ids":["SRC2"],"overlap":"Very close mechanism-level overlap: common physical excitation of a reference and adjustable element, differential mismatch sensing, polarity-correct pulses whose width reflects mismatch, repetition to convergence, and persistent resistive-state adjustment.","remaining_difference":"The reference is a passive ladder supplying predetermined scalar resistance levels and programming is element-selective. It does not transfer a characterized peer computing array's realized multi-line transfer surface, including coupled array effects, nor disclose staged decoupling, standalone held-out verification, or a second peer reference."},{"name":"Gradient-descent programming of complete analog in-memory-computing cores","source_ids":["SRC3"],"overlap":"Measures aggregate MVM response under multiple inputs and changes physical device states to minimize whole-core output error, addressing errors that per-cell target programming misses.","remaining_difference":"The target and corrective gradients are digitally computed; there is no simultaneously excited mentor array, direct analog error-current bridge, staged physical withdrawal, or secondary-reference anomaly check."},{"name":"Error-compensating multi-device precision programming","source_ids":["SRC4"],"overlap":"Compensates physical programming errors at the aggregate analog-computation level and demonstrates persistent programmed states on memristor hardware.","remaining_difference":"Compensation is internal to the target representation and relies on digital peripherals; it does not copy a removable reference array's realized transfer behavior through direct paired excitation."}],"prior_art_disposition":"ADJACENT_PRIOR_ART","contrastive_claim_remaining":"Relative to scalar reference-ladder write-and-verify and digitally optimized whole-core programming, a removable, purely analog bridge can use simultaneous probes of two complete arrays to convert their multi-line output-current mismatch directly into bounded local programming charge, producing lower held-out transfer-surface error that persists after staged weakening and complete disconnection; substituting a second characterized array can additionally expose a primary-reference-specific feature.","contrastive_claim_falsifier":"The claim is falsified if a prior disclosure demonstrates that same peer-array, simultaneous-response, direct-analog programming and post-disconnection bundle, or if the bounded experiment fails to reduce held-out standalone mismatch versus both pre-coupling and open-loop controls, loses the improvement after disconnection or retention, or shows that improvement is only temporary fixture loading or digital correction.","gates":{"adequate_source_search":{"status":"PASS","rationale":"The bounded screen covered direct phrasing, memristor/write-verify terminology, analog-computing practices, patents, and component combinations. Four opened sources span four publishers and include three primary research reports. This supports a coarse disposition but is not an exhaustive patent or literature search.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"supported_problem":{"status":"PASS","rationale":"Primary experiments establish device-to-device variability, stochastic programming response, and consequential aggregate MVM programming error, although the exact paired-whole-array manifestation is only partly supported.","source_ids":["SRC1","SRC3","SRC4"]},"distinct_testable_claim":{"status":"PASS","rationale":"The surviving distinction is operational and measurable: peer-array transfer of realized multi-line response by direct analog mismatch-driven programming, followed by staged removal, held-out standalone measurement, retention, and secondary-reference substitution. The closest source instead transfers scalar ladder values; whole-core rivals use digital targets and optimization.","source_ids":["SRC2","SRC3","SRC4"]},"bounded_next_test":{"status":"PASS","rationale":"One characterized reference, one sacrificial adjustable array, and one untouched open-loop control can be tested with predeclared coupling and held-out probes. Measurements before coupling, after each resistance stage, after disconnection, and after one retention interval directly distinguish persistent programming from temporary loading. Clamp events, heating, oscillation, error growth, or charge-budget approach are explicit stopping criteria.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"no_obvious_safety_or_authority_stop":{"status":"PASS","rationale":"No obvious categorical stop applies to a low-energy benchtop experiment on sacrificial compatible hardware under a hardware safety engineer's authority. Current limiting, fuses, voltage clamps, thermal cutoff, emergency disconnection, charge limits, and exclusion of production or irreplaceable hardware appropriately bound the first test; device wear and unintended state changes remain monitored experimental hazards.","source_ids":["SRC1","SRC2"]}},"screen_survival":true,"world_novelty_boundary":"This bounded public-web screen found close component-level and aggregate-programming prior art but no retained source containing the full peer-reference transfer and autonomy-release combination. It establishes only an ADJACENT_PRIOR_ART screening disposition, not world novelty, patentability, freedom to operate, market size, expert acceptance, or realized technical value."}