{"schema_version":1,"experiment_id":"eoa_inverse_innovation_exp12_substrate_denial72_20260805","research_id":"eoa_inverse_innovation_exp12_light_screen_20260805","cell_id":"backcasting_pathway_design__computer_science","search_lanes":{"direct_problem_and_intervention":{"queries":["storage controller power sequencing partial power brownout write corruption datasheet reset power rails","analog power sequencer window comparator MOSFET load switch dwell startup brownout reverse sequence"],"source_ids":["SRC1","SRC2"],"no_result_note":null},"synonyms_and_historical_terms":{"queries":["supply tracking supervisor brownout reset comparator capacitor delay MOSFET sequencing","power good daisy chain analog sequencer reset write protect clock valid"],"source_ids":["SRC2","SRC3"],"no_result_note":null},"products_practices_and_standards":{"queries":["hardware power sequencing IC monitor prerequisite rails fault shutdown reverse order datasheet","power supply sequence specifications power good discharge reverse order"],"source_ids":["SRC3","SRC4"],"no_result_note":null},"component_combination":{"queries":["analog hardware interlock multiple prerequisites power rails clock valid reset release","storage board power sequencer write enable inhibit undervoltage comparator"],"source_ids":["SRC2","SRC3","SRC4"],"no_result_note":"No retained source disclosed the exact combination of storage write-enable, clock-valid, reset, rail windows, and a removable daughtercard. The results nevertheless disclosed close combinations of condition-dependent rail gating, analog delay, reset control, MOSFET switching, undervoltage response, reverse sequencing, and discharge; absence of the full phrase is not treated as novelty evidence."}},"sources":[{"source_id":"SRC1","title":"Understanding the Robustness of SSDs under Power Fault","publisher":"USENIX Association","url":"https://www.usenix.org/conference/fast13/technical-sessions/presentation/zheng","source_type":"PRIMARY_RESEARCH","claims_supported":["Hardware fault-injection experiments applied more than 3,000 power-fault cycles to 15 commodity SSDs.","Thirteen tested SSDs exhibited failures including bit corruption, shorn or unserializable writes, metadata corruption, and total device failure.","Storage integrity and recoverability under power faults are empirically visible problems."]},{"source_id":"SRC2","title":"Multiple Voltage Systems Need Supply-Voltage Sequencing","publisher":"Analog Devices","url":"https://www.analog.com/en/resources/technical-articles/multiple-voltage-systems-need-supplyvoltage-sequencing.html","source_type":"OFFICIAL_GUIDANCE","claims_supported":["Improper supply order can cause latch-up or uncontrolled behavior in multivoltage systems.","A disclosed discrete circuit monitors an upstream supply, adds an RC delay, and drives a MOSFET so a downstream supply cannot appear before the upstream threshold is reached.","The guidance also discloses daisy-chained stages, downstream shutdown when an upstream supply fails, and reset sequencing that prevents slave activation without the master condition."]},{"source_id":"SRC3","title":"Power Supply Sequence Specification ①: Power Supply Sequence Specifications and Control Block Diagrams","publisher":"ROHM Semiconductor","url":"https://techweb.rohm.com/product/power-ic/dcdc/9900/","source_type":"OFFICIAL_GUIDANCE","claims_supported":["ROHM discloses condition-dependent startup in which each next rail starts only after the preceding rail reaches its target voltage.","It discloses reverse-order shutdown using power-good functions and discharge blocks that rapidly remove stored output charge.","The design process begins from specified target operations and determines the control blocks required to obtain them."]},{"source_id":"SRC4","title":"ISL8723 Power Sequencing Controllers","publisher":"Renesas Electronics","url":"https://www.renesas.com/en/products/isl8723","source_type":"FIRST_PARTY_PRODUCT","claims_supported":["The ISL8723/ISL8724 implements four-channel turn-on and turn-off sequencing with undervoltage fault protection.","It drives external MOSFET gates, permits daisy chaining, and uses external resistors and capacitors to program thresholds and ramp timing.","Its product description expressly addresses keeping all monitored rails minimally compliant before turn-on and maintaining that compliance during operation."]}],"problem_evidence":{"status":"PARTLY_SUPPORTED","finding":"The general problem is visible: controlled studies show serious SSD failures under power faults, while manufacturer guidance identifies improper multirail order, upstream-supply loss, and premature reset release as routes to latch-up or uncontrolled behavior. The bounded sources do not directly document the proposal's exact oscilloscope signature on a storage-bearing compute board—write-enable active while a specified rail, reference, clock-valid signal, or dwell condition is false—so that narrower causal formulation remains only partly supported.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"closest_prior_art":[{"name":"Discrete comparator–RC–MOSFET supply sequencer","source_ids":["SRC2"],"overlap":"Monitors an upstream voltage threshold, imposes analog dwell, physically gates a downstream rail with a MOSFET, supports cascading, and removes the dependent rail when its prerequisite disappears without firmware.","remaining_difference":"The disclosed examples do not present one removable storage-board daughtercard that jointly gates rail windows, reference, clock-valid, reset, and memory write-enable from a storage-specific backward dependency analysis."},{"name":"Power-good chain with reverse shutdown and active discharge","source_ids":["SRC3"],"overlap":"Derives control blocks from target sequence behavior, admits each downstream rail only after its predecessor reaches target voltage, shuts rails down in reverse order, and actively discharges their stored energy.","remaining_difference":"The guidance is a general rail-sequencing design rather than an expressly storage-writability-centered chain incorporating heterogeneous non-rail prerequisites."},{"name":"ISL8723/ISL8724 analog power-sequencing controller","source_ids":["SRC4"],"overlap":"Provides analog threshold monitoring, capacitor-programmed timing, MOSFET gate control, undervoltage protection, multi-stage cascading, and continued-compliance monitoring during operation.","remaining_difference":"It is an integrated four-rail sequencer and does not itself disclose the proposed discrete daughtercard or the exact clock-valid, reset, reference, and write-enable dependency map."}],"prior_art_disposition":"ESTABLISHED_PRACTICE","contrastive_claim_remaining":"On one specified storage-board fixture, a removable, microcontroller-free daughtercard that extends established condition-dependent analog power sequencing to the board's particular rail, reference, clock-valid, reset, and write-enable prerequisites will keep each dependent energy or write-enable node unavailable whenever any mapped predecessor is outside its declared window or dwell requirement, including during imposed bounce and brownout, and will withdraw dependent energy in the declared reverse order. The contrast is limited to that heterogeneous storage-specific implementation; analog prerequisite gating, dwell, cascading, reverse shutdown, and discharge are already established.","contrastive_claim_falsifier":"Under the predeclared transient matrix, the claim is falsified if any mapped predecessor is false while its dependent rail or write-enable remains active beyond the specified propagation or discharge allowance; if the daughtercard creates a partial-power state absent from baseline; or if an opened prior-art implementation is shown to enforce the same storage-specific rail/reference/clock/reset/write-enable dependency map on a removable, firmware-free board.","gates":{"adequate_source_search":{"status":"PASS","rationale":"The search covered the proposal directly, older terms such as supply tracking and supervisors, products and design practice, and combinations involving power-good, reset, clock-valid, write protection, MOSFET gating, dwell, and reverse discharge. Exactly four opened sources from four publishers were retained, including primary research and first-party or official material.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"supported_problem":{"status":"PASS","rationale":"Power-fault storage failures and hazards from invalid multirail sequencing are supported, although the exact proposed storage-board trace signature is not directly demonstrated; therefore the evidence is appropriately classified as partly supported.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"distinct_testable_claim":{"status":"PASS","rationale":"After removing established analog-sequencing elements, a narrow claim remains: simultaneous hardwired enforcement of a declared storage-specific set of rail, reference, clock, reset, dwell, and write-enable dependencies. Every prerequisite and dependent node can be probed, independently violated, and checked against explicit timing allowances.","source_ids":["SRC2","SRC3","SRC4"]},"bounded_next_test":{"status":"PASS","rationale":"A low-voltage dummy-load fixture, baseline comparator, predeclared ramp/bounce/brownout matrix, one-at-a-time prerequisite violations, and synchronized measurements of every stage form a bounded feasibility and falsification test. Hardware power-fault injection is also an established experimental method.","source_ids":["SRC1","SRC2","SRC3","SRC4"]},"no_obvious_safety_or_authority_stop":{"status":"PASS","rationale":"The proposed first test is confined to a removable low-voltage daughtercard, current-limited supply, dummy loads, ratings checks, explicit electrical-review authority, and defined de-energization and rollback conditions. Backfeed, thermal stress, and discharge behavior remain test hazards requiring the stated halt rules, but no obvious authority or safety stop precludes that bounded bench test.","source_ids":["SRC2","SRC3","SRC4"]}},"screen_survival":false,"world_novelty_boundary":"This screen finds the central comparator/threshold, analog-delay, MOSFET-gating, cascading, continued-compliance, reverse-shutdown, and discharge pattern to be established practice. It does not establish that the narrower storage-specific heterogeneous dependency map has or has not appeared elsewhere. This bounded public-web search cannot determine world novelty, patentability, freedom to operate, market size, expert acceptance, comparative performance, or realized value."}