{"schema_version":1,"experiment_id":"eoa_inverse_innovation_exp12_substrate_denial72_20260805","cell_id":"synchronized_release_dampening__computer_science","arm":"CONSTRAINED_MAX","candidate_id":"synchronized_release_dampening__computer_science__CONSTRAINED_MAX","decision":"PROPOSAL","abstention_reason":null,"proposal":{"schema_version":1,"experiment_id":"eoa_inverse_innovation_exp12_substrate_denial72_20260805","cell_id":"synchronized_release_dampening__computer_science","arm":"CONSTRAINED_MAX","candidate_id":"synchronized_release_dampening__computer_science__CONSTRAINED_MAX","proposal_index":1,"version":0,"title":"Firmware-Free Staggered Power-Restoration Backplane for Computing Racks","problem":"After a low-voltage DC computing rack loses and regains power, server, storage, or accelerator branches can begin charging input capacitors and starting fans or drives within the same short interval. The source may support every branch at steady state and each branch individually at startup, yet the overlapping startup transients can exceed its momentary current envelope, sag the bus, trip protection, or initiate a repeated brownout-and-restart cycle.","actors":["Rack-level low-voltage DC supply, distribution bus, wiring, and overcurrent protection","Server, storage, or accelerator modules connected as branch loads","Input bulk capacitors, fans, and drive motors that draw startup current","Rack owner and electrical-safety authority"],"observable_state":"Following one common bus-voltage restoration edge, branch-current onset times cluster narrowly; aggregate current rises while bus voltage reaches a coincident nadir, and modules may cross undervoltage thresholds, reset, or repeat the startup waveform. Relevant observables are first-to-last branch onset time, number of overlapping startup pulses, aggregate current, voltage nadir, protection state, and successful branch starts.","consequence":"A rack whose normal running load fits its source can nevertheless fail to restore computation or storage, cycle through repeated cold starts, or unnecessarily trigger upstream protection because transient demand is correlated in time.","affected_objective":"Reliable restoration of all computing branches within the existing steady-state electrical envelope while preserving protection, bounded startup delay, and equipment safety.","intervention":"Place a self-powered analog power-entry interposer between the rack DC bus and each branch. Interposers use deliberately different, tolerance-separated resistor-capacitor delay bands, an analog bus-voltage qualification threshold, a MOSFET slew/current limiter, a branch fuse, and a discharge path. A common voltage return starts every delay network, but their physical charge rates cause branch gates to conduct at separated times or in small cohorts. A not-yet-conducting branch remains inhibited while the bus is below the qualification threshold; once the bus remains healthy, every branch has a finite designed latest-start time. The device contains no microcontroller, firmware, network connection, software clock, or operator-paced release sequence.","structural_mapping":[{"archetype_element":"Shared Release Signal","domain_realization":"The common restoration edge of the rack DC bus after an outage or upstream reset."},{"archetype_element":"Waiting Population Boundary","domain_realization":"The finite set of unpowered computing branches attached to that bus, including their discharged input capacitors and stopped motors or fans."},{"archetype_element":"Finite Choke Point","domain_realization":"The transient-current envelope and source impedance of the rack converter, bus, connectors, wiring, and protective devices."},{"archetype_element":"Release Correlation Metric","domain_realization":"Measured distribution of branch-current onset times, simultaneous startup-pulse count, aggregate-current peak, and coincident bus-voltage nadir after restoration."},{"archetype_element":"Dispersion Policy","domain_realization":"Nonoverlapping analog RC delay bands convert one restoration edge into physically separated branch-enablement times."},{"archetype_element":"Admission Gate","domain_realization":"Each branch remains electrically disconnected until its threshold gate conducts; the MOSFET limiter then bounds current slew during admission."},{"archetype_element":"Capacity Recovery Signal","domain_realization":"Bus voltage is sensed directly by a nonprogrammable threshold circuit, which inhibits unopened branches while the source is below its healthy-voltage floor."},{"archetype_element":"Fairness and Starvation Guard","domain_realization":"Distinct but bounded delay values and non-retrying turn-on latches ensure that a continuously healthy bus eventually energizes every branch rather than repeatedly favoring an early branch."},{"archetype_element":"Herd Scenario Load Test","domain_realization":"A controlled common power-restoration step is applied to multiple capacitor-and-resistor branch emulators while branch currents and bus voltage are captured."}],"mechanism_mapping":[{"mechanism_slug":"jittered_wakeup_timer","role":"Deliberately unequal analog charge time constants provide firmware-free temporal dispersion of branch turn-on. The dispersion is fixed and tolerance-bounded rather than generated by software randomness.","counterfactual_removal":"If the delay networks are bypassed or made equal while retaining the same per-branch current limiter, branch gates again conduct together and the archetype-specific reduction of release correlation disappears."},{"mechanism_slug":"capacity_aware_reconnect_queue","role":"Unopened branches constitute a physical waiting set: their voltage-qualified gates admit them only after their assigned delay and only while the bus remains above its analog health threshold.","counterfactual_removal":"If voltage qualification is bypassed, later branches enter on elapsed time even when an earlier cohort has not allowed the bus to recover, so unexpected startup duration can recreate overlapping demand despite nominal staggering."}],"causal_chain":["An outage removes bus voltage, discharges branch input capacitors, and leaves multiple computing loads awaiting the same restoration event.","The restored bus crosses similar power-supply turn-on thresholds across branches within a narrow interval.","Capacitor charging and motor or fan acceleration currents therefore overlap.","The overlapping current interacts with finite source impedance or protection, producing a voltage sag, trip, or reset that can restart the same cycle.","Distinct RC networks accumulate charge at different physical rates from the same restored voltage.","Their threshold devices enable branch MOSFETs at separated times, while slew limiting shapes each admitted startup pulse.","Analog undervoltage qualification holds unopened branches when the source has not remained healthy after an earlier admission.","Temporal separation permits earlier startup current to decay before later branches enter, reducing the overlap presented to the choke point without changing the running workload.","If the source remains healthy, bounded delay values cause every branch to energize and the rack completes restoration."],"baseline":"Every branch is directly exposed to the restored bus and follows its own similar undervoltage lockout or soft-start behavior. Existing fuses and breakers respond only after current is drawn, and identical per-supply soft-start ramps can remain correlated because they begin from the same voltage edge.","nearest_rivals":["Increase the transient rating of the rack converter, UPS, PDU, wiring, and protection so all startup pulses can be served simultaneously.","Redesign every load power supply to reduce its individual inrush or lengthen its soft-start ramp, without intentionally differentiating branch start times.","Add local hold-up or startup energy storage so branch transients are not drawn directly from the shared bus.","Partition branches across genuinely independent power feeds or converters so simultaneous starts do not share one choke point.","Use a programmable sequencer or network-coordinated boot controller; this can stage loads but makes computation or software part of the operative release path."],"remaining_contrastive_claim":"The bounded hypothesis is conditional: when each branch startup and the combined steady-state load fit the source but overlapping startup transients do not, unequal physical delay bands plus bounded current slew should decrease startup overlap and improve the bus-voltage nadir relative to both direct reconnection and identical-delay soft-start under the same source and loads. The proposal does not address steady overload, a source that cannot start one branch, or a defective branch.","authority_safety":{"decision_authority":"The laboratory owner and electrical-safety lead may authorize the isolated low-voltage test. Any production deployment additionally requires the rack owner, facilities electrical authority, and applicable equipment or certification owner.","authorized_first_step":"Construct and test only a fused, current-limited 24 V DC bench containing load emulators and removable prototype interposers; characterize direct, uniform-soft-start, and phase-spread configurations without connecting production equipment.","excluded_actions":["Connection to building mains, facility UPS equipment, production PDUs, or production computing racks","Bypassing fuses, breakers, protective earth, power-supply protections, or safety interlocks","Modification of certified or warranty-sealed power supplies","Unattended energization or operation beyond component voltage, current, power, or temperature ratings","Delaying or switching life-safety, emergency-shutdown, or otherwise safety-critical loads"],"halt_rollback":"De-energize immediately on component overheating, smoke, insulation damage, out-of-rating current, persistent undervoltage, missed branch starts, or repeated gate cycling. Discharge every capacitor through rated bleeders, verify zero stored voltage, and remove the plug-in interposers; direct reconnection of the emulator branches restores the bench baseline."},"negative_tests":{"strongest_counterevidence":"The synchronization diagnosis is undermined if one branch alone or the combined steady load trips the source, or if branch startup currents are already spread beyond their pulse duration while the same sag or trip persists.","problem_falsifier":"Controlled restoration measurements show no narrow common onset cluster before the failure, or the bus still reaches the failure condition after all but one startup branch is removed.","intervention_falsifier":"With source impedance and loads held fixed, unequal analog delay bands fail to widen the branch-onset distribution, reduce simultaneous startup overlap, or improve the voltage nadir relative to the same current limiters with equal delays; the intervention also fails if any healthy branch misses its bounded start window or the voltage gate produces oscillatory reconnects.","risks":["RC values, thresholds, and MOSFET behavior can drift with tolerance, temperature, and aging until nominally separated delay bands overlap.","A switch can fail open and strand a branch, or fail short and restore simultaneous admission.","Series devices can dissipate excessive heat, add voltage drop, or introduce electrical transients and electromagnetic interference.","Voltage-qualified gates can oscillate around a marginal source threshold and create a new repeated release wave.","Fixed ordering can delay management, storage-recovery, or dependency nodes whose earlier availability is operationally important.","Staggering can conceal an undersized source or steady overload rather than correct it.","Adding interposers can invalidate equipment safety certification or create connector and maintenance hazards."]},"next_evidence_step":"On one isolated, fused, current-limited 24 V DC bench, connect eight identical capacitor-plus-resistor branch emulators to a source whose ratings support one startup and the combined steady draw. Before energization, specify component limits and a maximum acceptable branch-start delay. Run ten restoration cycles for each removable configuration: direct simultaneous connection, equal-delay per-branch slew limiting, and tolerance-separated analog delay bands with the same slew limiting. Capture every branch-current onset, aggregate current, bus-voltage nadir, switch temperature, missed starts, and reset cycles with current probes and an oscilloscope. Advance the causal claim only if the phase-spread configuration widens onset timing, reduces overlap, and improves voltage recovery without late or missed starts, oscillation, or out-of-rating heating; otherwise halt.","prior_art_status":"UNSEARCHED","diversity_from_prior_proposals":"Not assessed against other proposals under runtime isolation. This candidate was derived only from the supplied record and realizes synchronized-release dampening through rack-level electrical-energy staging rather than software coordination.","revision_record":{"parent_version":null,"progress_targets_addressed":["Make the essential intervention independent of software, analytics, governance, and operator sequencing","Preserve the shared trigger, waiting population, finite choke, dispersion, admission, and recovery-signal causal structure","Distinguish temporal-correlation control from source expansion and uniform soft-start","Provide a bounded physical bench test with direct causal contrasts, safeguards, and falsifiers"],"conceptual_changes":["Initial version; no parent proposal.","Located the domain problem at the physical power-restoration boundary of a computing rack.","Defined release correlation, rather than total running power, as the conditional defect."],"operational_changes":["Specified removable analog branch interposers with unequal RC delay bands, voltage qualification, slew limiting, fusing, and discharge paths.","Restricted the first action to an isolated low-voltage emulator bench and excluded production or mains deployment."],"evidence_changes":["Specified direct-connect and equal-delay soft-start controls to isolate the contribution of temporal dispersion.","Specified branch-onset, overlap, aggregate-current, voltage-nadir, thermal, missed-start, and oscillation observations."],"claim_changes":["Claims are framed as a falsifiable conditional mechanism hypothesis.","No claim is made about novelty, prevalence, demand, prior art, or effect size."]},"substrate_contract":{"primary_allowed_process":"PHYSICAL_MATERIAL","counterfactual_independence":"The essential process is electrical-energy flow through material components: restored voltage charges physically different RC networks, semiconductor thresholds conduct at different times, and MOSFET impedance limits branch current slew. If all firmware, software scheduling, algorithmic inference, network messaging, telemetry, reporting, permissions, operator sequencing, and procedural enforcement are removed after installation, the same voltage step still produces separated branch conduction and current shaping.","forbidden_channel_audit":"No microcontroller, software clock, model, database, dashboard, recommender, communications path, incentive, authorization decision, or human release procedure lies in the operative causal path. Oscilloscope measurements are evidence collection only. Installation approval and electrical safeguards constrain use but do not generate the effect. The intervention would continue to stagger restoration in an unmonitored enclosure solely through charge accumulation, voltage thresholds, semiconductor conduction, and circuit impedance."}}}