Digital Logic & Boolean Networks

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Abstractions about logic gates, sequential circuits, Boolean networks, hardware-description synthesis, and optimization of digital logic.

9 abstractions in this family — domain-specific abstractions that sit near one another in structural-signature space (k-means over structural-signature embeddings). Each is shown with its short description.

• And-inverter graph — A directed acyclic representation of Boolean logic using two-input AND nodes and optional edge inversions.
• Boolean network — A discrete dynamical system of Boolean variables whose values update according to assigned Boolean functions of other network nodes.
• C-element — An asynchronous state-holding logic element whose output changes only when all inputs agree and otherwise retains its prior state.
• Flow to HDL — A hardware-design translation workflow that compiles a flow-based or dataflow system model into synthesizable hardware-description-language structure.
• Fredkin gate — A reversible three-bit controlled-swap gate that preserves the control bit and swaps the other two bits exactly when the control is active.
• Logic gate — A functional element that maps one or more logical input values to an output value according to a Boolean operation.
• Logic optimization — Transformation of a digital logic network into a functionally equivalent representation that better satisfies area, delay, power or implementation constraints.
• Sequential logic — Digital logic whose outputs depend on both current inputs and stored state representing prior input history.
• XOR gate — A digital logic gate that outputs true exactly when an odd number of its binary inputs are true, implementing exclusive disjunction and two-input inequality.