Memory Organisation¶

The arrangement of memory banks, word widths, addressing, and buses that governs how computer main memory supplies data and programs to a cache.

Version: v1 · 2026-09-28 · History
Domain-specific #: 10665
Domain group: Applied Sciences & Engineering
Origin domain: Computer Science & Software Engineering
Subdomain: Computer Architecture → Computer Science & Software Engineering
Aliases: Memory Organization

Core Idea¶

Memory organisation is the physical-and-logical arrangement by which a computer's main memory serves the cache: word width, bank structure, address-to-bank mapping, buses, and selection logic jointly determine what data can move on an access.

One-word-wide, wide, and interleaved arrangements do not merely rename capacities. They offer different combinations of transfer width and bank activity, and their performance depends on request patterns and timing rather than on bank count alone.

Structural Signature¶

Sig role-phrases:

Storage banks — Hold the words whose physical grouping defines potential concurrent service. It is necessary. Counterfactual: Changing the number or structure of banks changes access opportunities.
Word and bus width — Sets how many data bits or words can move across an interface per transfer. It is necessary. Counterfactual: A wider bank without a correspondingly usable path does not deliver a wider cache transfer.
Address-to-bank mapping — Selects where successive addressed words reside. It is central to interleaving. Counterfactual: Changing low-order-bit assignment changes which sequential requests hit separate banks.
Cache interface — Receives selected words or blocks and makes organization visible as transfer behavior. It is necessary in this source scope. Counterfactual: An unconnected array does not explain the source's cache-facing comparison.
Selection and transfer control — Chooses the bank or bus path and sequences delivery under an access request. It is operating role. Counterfactual: Without selection, bank multiplicity and width do not establish usable access.

What It Is Not¶

Not memory capacity. Equal-size memories can have different banks and transfer paths.
Not the entire memory hierarchy. Cache-versus-main-memory placement is a different axis from main-memory bank and bus arrangement.
Not a speed guarantee. More banks or wider buses help only when controller timing and workload use them.
Not software data layout alone. The source concerns architectural storage and transfers, not the order of fields in a record.
Closest near-miss. Memory hierarchy ranks storage levels by latency and capacity; memory organisation here concerns how the main-memory units and transfer paths are arranged within one level's interface.

Scope of Application¶

Computer architecture. Compares cache-facing main-memory arrangements by bank, width, and interconnect.
Memory-controller design. Determines address mapping and selection needed to serve requests.
Cache-line transfer. Relates word or bus width to the transfers required for a requested block.
Performance analysis. Tests whether bank interleaving and access patterns actually permit overlap.

Clarity¶

Specify whether 'wide' refers to a chip, bank, bus, or entire module; state word and cache-line sizes, bank count, address-bit mapping, number of buses, selection hardware, controller timing, and the request sequence. This resolves the common conflation of stored capacity, one-transfer data width, and sustainable access throughput.

Manages Complexity¶

A memory access traverses addresses, banks, buses, multiplexers, and cache ports. The organization abstraction reduces these details to two key questions—where is the requested word and how wide/available is the path—while retaining timing constraints needed to avoid an automatic speed claim.

Abstract Reasoning¶

Identify the cache request size and sequence to be served.
Map each address to a bank and the word position within it.
Trace the available bus and selection path for each word or block.
Compare the number of transfers and possible bank overlaps under controller timing.
Evaluate throughput and latency for the actual access pattern, not from architecture labels alone.

Knowledge Transfer¶

The bank–mapping–path analysis transfers literally among compatible computer memory implementations, including one-word, wide, and interleaved designs. The prime interleaving describes alternating assignment more broadly, but it does not carry the full cache-facing bus and controller semantics of this domain-specific organisation.

Examples¶

Canonical¶

In the one-word-wide arrangement described in the source, a one-word memory output is connected by a one-word bus to cache. A cache request therefore obtains only that word per bus transfer; a wider cache line needs additional transfers, subject to controller behavior.

Mapped back: Storage banks → one-word delivery unit; Word and bus width → one word; Address-to-bank mapping → requested word selected; Cache interface → one-word path; Selection and transfer control → repeated transfers for a larger block.

Applied / In Practice¶

In the source's interleaved arrangement, sequential addresses are distributed across several one-word banks by low-order address bits. Successive accesses can engage different banks, so overlapping bank activity may raise throughput when timing and bus service permit; bank count alone guarantees nothing.

Mapped back: Storage banks → several one-word modules; Word and bus width → one-word bank paths; Address-to-bank mapping → low-order-bit bank selection; Cache interface → receives selected words; Selection and transfer control → bank selection on each access.

Structural Tensions¶

T1 — Transfer Width versus Hardware Path Cost. A wide memory and bus can move more words per transfer, but wider pathways and selection networks consume hardware resources and may not help access patterns that use few words.

Diagnostic: Does the workload benefit from wider delivered blocks enough to justify the path?

T2 — Bank Parallelism versus Contention And Sequencing. Interleaving can keep modules active across successive addresses, but correlated address patterns, shared paths, or controller limits can still serialize service.

Diagnostic: Which accesses actually reach independent banks at the relevant time?

Structural–Framed Character¶

A provisional portable skeleton is partitioning stored words among transfer paths. Here address selection, banks, bus widths, controller timing, and cache-line delivery make that pattern computer-specific; interleaving is only one variant.

Evaluative weight: Low; speed and cost are separate judgments. Human-practice-bound: Moderate: architects choose mappings under physical timing constraints. Institutional origin: Hardware interface conventions matter, but no single authority constitutes the arrangement. Vocabulary travels: Bank/path analysis spans machines; generic resource interleaving lacks cache semantics. Import versus recognize: Recognize an instance by address-to-transfer organization; calling any alternating allocation “memory organisation” imports the computer carrier.

Its character: A hardware-bound arrangement with a portable partition/scheduling pattern.

Structural Core vs. Domain Accent¶

Skeletal core. Partition items among channels and route them to a consumer under a schedule.

Domain-bound accent. Address bits, memory banks, word and bus widths, controllers, cache lines, and access timing determine computer memory organisation.

Why not prime. Partition and interleaving travel widely; the named node requires cache-facing address and transfer semantics that do not.

This entry presupposes Data Structure.

Recorded DAG status — approved unparented root. The accepted node is the whole cache-facing memory arrangement, not only the interleaved variant; no necessary parent is asserted by this repair.
Related prime — interleaving. Alternating addresses among banks is one architectural instance of interleaving, but wide and one-word arrangements show why the prime is not a synonym for the whole node.

Relationships to Other Abstractions¶

Current abstraction Memory Organisation Domain-specific

Parents (1) — more general patterns this builds on

Memory Organisation presupposes Data Structure Prime

Memory organization presupposes structured addressing and arrangement of stored data words.

Hierarchy path (1) — routes to 1 parentless root

Memory Organisation → Data Structure → Trade-offs → Constraint

Neighborhood in Abstraction Space¶

Memory Organisation sits in a moderately populated region (46^th percentile for distinctiveness): it has near-neighbors but no dense thicket of look-alikes.

Family — Computer Systems & Network Architecture (20 abstractions)

Nearest neighbors

Computed from structural-signature embeddings · 2026-10-08

Not to Be Confused With¶

Memory hierarchy. Tell: Is the question about storage levels or about bank/width/bus arrangement within the main-memory interface?
Memory capacity. Tell: Does the claim specify how a word is selected and transferred, rather than only how much is stored?
Cache replacement. Tell: Does the mechanism decide which cached block to evict, rather than how main memory sends a word?
Interleaving alone. Tell: Are non-interleaved one-word and wide arrangements also within the scope being described?

References¶

Frozen Wikipedia discovery revision: https://en.wikipedia.org/wiki/Memory_organisation (revision 1274414957).
Preserved source candidate: https://www.geeksforgeeks.org/memory-hierarchy-design-and-its-characteristics/

The frozen Wikipedia revision is discovery provenance. The retained source set was reviewed for identity, formal or operational relation, and scope. The encyclopedia's structural synthesis is bounded to those claims; a thin authority surface is recorded as a nonblocking source-strengthening repair rather than concealed.