Memory Rank¶

Group DRAM devices behind one chip-select so they activate together and contribute parallel bit lanes to one logical data-width unit on a memory channel.

Version: v2 · 2026-09-06 · History
Domain-specific #: 2260
Origin domain: computer science
Subdomain: computer architecture
Aliases: DRAM rank, DIMM rank

Core Idea¶

A memory rank is a set of DRAM devices that share a chip-select and are activated as one logical unit. The devices contribute parallel bit lanes so their combined interface supplies the channel data width for an access—classically 64 data bits on a non-ECC DIMM, with additional lanes when error correction is present. Other command and address signals are commonly shared across ranks; chip select determines which rank responds.^[1]

A module may contain one or more ranks, and a channel can carry ranks across multiple modules. Rank count is logical/electrical, not reliably inferred from whether chips are mounted on one or two physical sides. More ranks can increase capacity and offer rank-level scheduling opportunities, but they add electrical loading and remain constrained by controller, module, and DRAM-generation rules.

Structural Signature¶

The memory channel. Shared command, address, and data wiring connects controller and modules.
The chip-select identity. One selection signal names the logical rank.
The parallel DRAM devices. Several chips respond simultaneously.
The per-device width. Each device contributes a fixed subset of data bits.
The aggregate rank width. Parallel contributions meet the channel's logical data width, including optional ECC lanes.
The shared access. One command targets corresponding locations across the selected devices.
The inactive-rank isolation. Unselected ranks do not drive the data bus.
The loading and scheduling envelope. Rank count affects timing, signal integrity, capacity, and interleaving.

What It Is Not¶

Not a DRAM bank. Banks are independently timed storage arrays inside a device or rank-level ensemble.
Not necessarily one memory module. A DIMM can contain multiple ranks.
Not a physical side of a DIMM. Single-/double-sided packaging does not determine logical rank count.
Not a memory channel. Multiple ranks can share one channel.
Not a CPU rank or hierarchy level. The term is specific to DRAM selection topology.
Not always accessible simultaneously with another rank. Conventional controllers select one rank for a transfer unless a newer architecture explicitly changes the interface.

Scope of Application¶

Memory rank is literal in DRAM module organization, channel design, controller scheduling, and system configuration.

DIMM specification. Reporting single-, dual-, quad-, or higher-rank organization.
Capacity design. Combining device density and width into module capacity.
Memory-controller scheduling. Alternating ranks to hide timing constraints.
Signal integrity. Budgeting command/address loading across ranks.
ECC organization. Adding parallel devices to supply check-bit lanes.
Performance diagnosis. Separating rank, bank, channel, and module effects.

Clarity¶

State memory generation, module type, channel width, ECC status, rank count, and device width. Explain how chip selects partition devices and how their lanes sum to the rank width. Use labels such as 2R×4 only with those definitions. Do not infer rank from visual chip placement or transfer performance rules from another generation.

Declare channel width, device data width, error-correction lanes, chip-select organization, and module topology. A rank is a logical activation group, not a visible side of a module; devices on both sides can belong to one rank, and one side can contain parts of more than one organization. Distinguish rank from bank, bank group, row, channel, subchannel, and DIMM. Shared command or address wiring does not mean all installed ranks respond to every access, because chip select gates participation. Capacity is the product of several hierarchy levels and cannot be inferred from rank count alone. Registered, buffered, stacked, or specialized memory can alter signal topology while retaining the logical concept. Vendor labels such as single-rank and dual-rank should be checked against actual organization rather than package appearance.

Manages Complexity¶

Rank abstracts many DRAM packages into one controller-visible selection and data unit. It lets capacity, timing, and command scheduling be reasoned about without tracking each chip separately. The abstraction hides physical layout and internal banks; debugging fails when rank, bank, DIMM, and channel are collapsed into one notion of 'memory row.'

A memory channel is wider than an individual DRAM device, so several devices must cooperate in parallel for one transfer. Rank groups those lanes behind one activation choice, turning many chips into one logical width unit. This organization separates spatial parallelism within a rank from temporal selection among ranks. Controllers can alternate available ranks to hide some timing constraints, but activating more devices also affects electrical loading, energy, and scheduling. Banks provide internal concurrency inside devices and are orthogonal to rank selection; conflating them obscures which resource is busy. The abstraction manages a nested hierarchy—channel, module, rank, device, bank, row—by assigning each level a distinct selection signal and concurrency role. Performance claims must therefore name the hierarchy level rather than crediting ‘more ranks’ universally.

Abstract Reasoning¶

Fix the channel interface and required data width.
Record each DRAM device's bit width and density.
Group enough devices to supply the channel width under one chip select.
Add check-bit devices if ECC is used.
Partition additional capacity into separately selected ranks.
Check controller rank limits and electrical loading.
Schedule commands with rank and bank timing distinguished.
Validate the logical organization from SPD or platform data.

Knowledge Transfer¶

The strict parent is Composition: multiple narrow devices are arranged into one wider logical unit whose behavior depends on coordinated activation. Parallelism is related, but rank identity also requires shared selection and unified controller visibility. Outside DRAM, 'rank' has unrelated mathematical and hierarchical meanings.

Composition is the strict parent because a rank combines parallel component lanes into a logical interface with a width none of the selected devices supplies alone. The transferable pattern is select component group together → concatenate simultaneous contributions → expose one composite unit. It resembles striping, but the DRAM residual includes chip select, synchronized commands, data-lane width, timing, banks, and channel electrical constraints. A collection of chips on a board is not enough; they must activate as the same logical selection unit. Transfer fails when components are merely redundant or independently addressed rather than composing one access width.

Examples¶

Canonical¶

A non-ECC 64-bit rank built from ×8 DRAM devices uses eight devices under one chip select. On an access, all eight receive the command and each contributes eight data bits, jointly filling the 64-bit interface. A second set of eight under another select makes the module dual-rank rather than widening the first rank.^[1]

Mapped back: eight ×8 devices + common select → simultaneous activation → eight parallel lanes → one 64-bit rank.

Applied / In Practice¶

A server upgrade compares two modules with equal total capacity but different rank organization. The platform engineer reads SPD data, checks the controller's supported ranks per channel, models command/address loading, and benchmarks rank interleaving. Chip placement on the PCB is ignored because it is not a reliable logical topology indicator.

A system reports a data-width mismatch between a module label and the number of visible packages. The engineer reconstructs the logical organization from device width, error-correction lanes, chip-select signals, and stacking rather than counting board sides. Two modules with identical capacity can expose different rank counts, changing how the controller schedules around refresh and activation delays. A benchmark improvement after adding ranks is interpreted conditionally: it may reflect rank-level interleaving under that workload, while another platform may be limited by command rate or electrical loading. The example shows why rank is an addressing-and-composition abstraction, not a synonym for capacity or speed.

Mapped back: module metadata → rank topology → controller/loading constraints → scheduling opportunity → validated configuration.

Structural Tensions¶

Capacity vs. electrical loading. More ranks add addressable storage but burden shared signals. Diagnostic: Does the channel remain inside its supported load and speed envelope?
Parallel width vs. single selection. Devices act together within a rank while ranks share and contend for buses. Diagnostic: Which level is actually parallel?
Logical organization vs. physical appearance. PCB sides are visible but unreliable. Diagnostic: Is rank count taken from interface metadata?
Interleaving opportunity vs. timing complexity. Multiple ranks can hide delays while adding scheduler constraints. Diagnostic: Does the controller exploit the topology?
Autonomous rank vs. generic composition. Composition travels; shared chip-select and bus width define the DRAM construct. Diagnostic: Are device lanes coordinated as one memory-access unit?

Structural–Framed Character¶

Memory rank is structural-leaning. Electrical topology and simultaneous activation are physical; channel width, labels, and standards are engineered conventions. It is evaluatively neutral and institutionally standardized but not socially constituted in operation. Composition supplies the portable structure; DRAM protocols and timing keep the construct domain-specific.

Shared rank selection, coordinated device activation, parallel lane contribution, one logical channel-width unit, and separation from banks and channels are structural. Device width, package count, error-correction provision, module side, buffering, data rate, and vendor naming are framed. A rank can span packages that look physically separate, and visually co-located packages can belong to different ranks. The controller's scheduling policy affects performance but not identity. This structural–framed split permits hardware variants to be compared without turning a packaging convention into the definition. It also keeps logical width distinct from aggregate capacity.

Structural Core vs. Domain Accent¶

The skeleton is narrow components + shared selector + parallel activation → one wider logical unit. The accent is DRAM devices, chip-select pins, DIMMs, data lanes, ECC, controller timing, and signal loading. Removing them yields generic composition or parallel assembly.

Composition is the strict parent because a rank combines multiple devices into a cohesive controller-visible unit with properties determined by their arrangement. Parallelism is related but does not alone express shared chip selection and aggregate width.

The prospective workspace queue contains one strict upward edge to prime:composition. No live DAG mutation is authorized.

Relationships to Other Abstractions¶

Current abstraction Memory Rank Domain-specific

Parents (1) — more general patterns this builds on

Memory Rank is a kind of Composition Prime

Composition is the strict parent because a rank combines multiple devices into a cohesive controller-visible unit with properties determined by their arrangement.

Hierarchy path (1) — routes to 1 parentless root

Memory Rank → Composition → Gestalt Principles → Holism

Neighborhood in Abstraction Space¶

Memory Rank sits in a sparse region of the domain-specific corpus (96^th percentile for distinctiveness): few abstractions share its structure, so a faithful description tends to retrieve it precisely.

Family — Unclustered & Miscellaneous (1565 abstractions)

Nearest neighbors

Computed from structural-signature embeddings · 2026-09-08

Not to Be Confused With¶

DRAM bank. An internal array/timing resource rather than a chip-selected device group.
Memory channel. The controller bus that can host multiple ranks.
DIMM. A physical module that can contain one or more ranks.
Memory row. An activated wordline within a bank.
Single- or double-sided module. Physical packaging labels that need not equal rank count.

References¶

[1] Bruce Jacob, Spencer Ng, and David Wang, Memory Systems: Cache, DRAM, Disk (Morgan Kaufmann, 2008), chapters 10–14. registry ↩a ↩b