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Moore's law

The empirical observation that transistor count per economically optimal integrated circuit doubles roughly every two years — a self-fulfilling industry roadmap that coordinated investment across the semiconductor supply chain so the complementary inputs for each process node arrived together.

Core Idea

Moore's law is the empirical observation first published by Gordon Moore in a 1965 Electronics article and revised in a 1975 IEDM paper: that the number of transistors on an economically optimal integrated circuit doubles approximately every two years (annually in the 1965 original; revised to biennial in 1975 as yield and economics were better understood). The proximate mechanism during the law's productive era was the combination of photolithographic feature shrinkage — each process generation reduces minimum feature dimensions, packing more transistors per unit area at equivalent yield — and gradual expansion of economically viable die size as defect density management improved. Dennard scaling complemented the transistor-count trend by showing that voltage and current could also be reduced proportionally with feature size, keeping power density approximately constant so that denser chips were not hotter chips. When Dennard scaling broke down around 2005 at sub-100nm nodes — leakage currents made further voltage reduction impractical — the power constraint became binding, clock frequencies stalled, and the industry pivoted to multi-core parallelism and specialization (GPUs, TPUs, NPUs) to continue extracting performance from a still-growing transistor budget. What distinguishes Moore's law from a simple empirical regularity is that it became a self-fulfilling industry roadmap: codified into the International Technology Roadmap for Semiconductors (ITRS, 1992–2016) and its successor the IRDS, it coordinated the timing of investments across chip designers, equipment makers (ASML, Applied Materials, Lam Research), photoresist and materials suppliers, and EDA tool vendors so that the complementary inputs required for each new process node were all ready simultaneously. The forecast shaped the investment that shaped the outcome. By the 2020s raw transistor density was clearly slowing below the historical doubling rate for leading-edge planar CMOS, while the industry continued progress on alternative axes — chiplet integration, 3D stacking (SRAM over logic), gate-all-around transistor geometries, advanced packaging — marking the transition to what practitioners call the "More than Moore" era.

Structural Signature

Sig role-phrases:

  • the count cadence — transistor density per economically optimal die doubling on a ~2-year schedule, the focal regularity held distinct from clock speed, energy-per-operation, or delivered performance
  • the lithographic mechanism — photolithographic feature shrink plus expanding economically viable die size, the proximate physical source of the density gains
  • the industry roadmap — the ITRS/IRDS coordination device that turns the cadence expectation into a shared plan participants resource against
  • the complementary inputs — EDA tools, design libraries, photoresists, lithography equipment, and fab capacity that must advance in lockstep so each node's budget arrives on time
  • the self-fulfilling loop — the forecast shaping the coordinated investment that produces the outcome, the endogenous character explaining a durability bare physics would not
  • the per-generation binding constraint — the single limiter (yield, defect density, lithographic resolution, leakage, interconnect) the next coordinated push must relax at each node
  • the axis-shift / saturation tail — the post-Dennard, "More than Moore" regime where raw density slows and progress migrates to parallelism, specialization, 3D stacking, and gate-all-around geometries

What It Is Not

  • Not a law of physics. No physical principle requires transistor count to double on a schedule; the doubling is an empirical, economic trajectory the industry coordinated to produce. It held because chip designers, lithography and materials suppliers, EDA vendors, and fabs invested against a shared ITRS/IRDS roadmap so the complementary inputs for each node arrived together — a self-fulfilling forecast, not a constant of nature.
  • Not a claim about clock speed, performance, or efficiency. What doubles is transistor density per economically optimal die, nothing else. Clock frequency, energy per operation, and delivered performance ride on separate axes — a distinction that became decisive when Dennard scaling broke around 2005: frequency stalled while transistor count kept climbing, and reading speed off the same curve misdescribes the era entirely.
  • Not over because the doubling slowed. Raw planar-CMOS density slowing below the historical rate is a change of axis, not the end of progress: the budget keeps growing while gains migrate to multi-core parallelism, specialization (GPUs, TPUs, NPUs), 3D stacking, gate-all-around geometries, and advanced packaging — the "More than Moore" regime. The curve reaching a limit on one axis is read as the constraint that matters shifting, not as collapse.
  • Not a guaranteed timetable that always holds. The cadence is conditional on the coordination continuing to relax whatever constraint is currently binding — yield, defect density, lithographic resolution, leakage, interconnect. When the old coordinated shrink no longer touches the binding constraint, the cadence stalls; it is sustainable only as long as the coordinated investment keeps working, not by force of the trend line itself.
  • Not the same mechanism wherever "Moore's law for X" is invoked. Applied to genome-sequencing cost, solar PV, or battery cost, the phrase usually borrows the exponential shape while dropping the lithography-plus-coordination machinery that gave the original its durability. Some of those curves do share an industry-coordinated learning-curve dynamic, but that shared content travels as the general primes, not as Moore's law — the semiconductor apparatus does not come with the name.
  • Not Dennard scaling. Dennard scaling is the complementary claim that voltage and current fall with feature size so power density stays roughly constant; it is what kept denser chips from being hotter chips. It broke down around 2005 while transistor-count doubling continued for years — so collapsing the two erases exactly the divergence (more transistors, but power-constrained) that defines the post-2005 history.

Scope of Application

Moore's law lives within the semiconductor industry and the broader computing economy that builds to its cadence; its reach is bounded there — the "Moore's law for X" invocations elsewhere either share the underlying machinery as co-instances (carried by learning_curve, coordination_problem_and_equilibrium_selection, and self_fulfilling_prophecy) or are mere exponential-shape analogy.

  • Semiconductor industry roadmapping — the home turf, where the ITRS (1992–2016) and successor IRDS codify the cadence into a shared plan that coordinates chip designers, lithography- and materials-suppliers (ASML, Applied Materials, Lam), photoresist and EDA-tool vendors, and fab operators so each node's complementary inputs arrive together.
  • Microprocessor and chip architecture — lets designers commit to transistor-budget-dependent architecture (out-of-order execution, deeper pipelines, larger caches, SIMD units) before the silicon exists, and frames the post-2005 pivot to multi-core parallelism and specialization (GPUs, TPUs, NPUs) as a change of axis.
  • Fab capital-expenditure planning — sets the process-node cadence and plant-capacity timing for Intel, TSMC, and Samsung and the equipment-supplier roadmaps that must advance in lockstep.
  • Computing-economics and productivity analysis — used (and frequently misused) as the benchmark for technological progress in Solow-residual decompositions and total-factor-productivity debates (Nordhaus on computing costs, Brynjolfsson and McAfee).
  • Strategic and venture-capital forecasting — serves as a default cadence expectation for adjacent technologies (storage, bandwidth, sensors, ML compute), pacing investment against a presumed capability doubling.
  • Adjacent doubling-laws cluster — supplies the borrowed cadence shape for Koomey's (energy efficiency), Kryder's (areal density), Cooper's (spectrum efficiency), and Edholm's (telecom bandwidth) laws, each its own substrate-specific regularity read as "Moore's-law-like."

Clarity

Moore's law's sharpest clarification for the semiconductor industry is that the doubling is not a passive fact of physics that the industry merely observes, but a coordination device it builds to — and naming it that way separates two readings that otherwise blur. "Capability improves exponentially because the underlying technology permits it" makes the trajectory exogenous, something to forecast and wait for; "capability doubles on schedule because chip designers, lithography and materials suppliers, EDA vendors, and fabs all invested against a shared roadmap so the complementary inputs for each node arrived together" makes it endogenous, something the industry's own coordinated investment produces. Once codified into the ITRS/IRDS roadmap, the forecast shaped the investment that shaped the outcome — and seeing that is what lets a strategist treat the cadence as a plan to be resourced rather than a free gift, and explains why the trend held for decades where uncoordinated exponentials stall.

The law also sharpens what, precisely, is doubling, which keeps the count axis distinct from the others a chip improves along: transistor density per economically optimal die is the focal regularity, not clock speed, energy per operation, or delivered performance — distinctions that became decisive once Dennard scaling broke around 2005, frequency stalled, and progress migrated to parallelism, specialization, 3D stacking, and gate-all-around geometries while raw density slowed. Holding the count metric separate is what makes the "More than Moore" transition legible as a change of axis rather than the end of progress. And the law's per-generation structure licenses a recurring diagnostic question: at this node, which single constraint — yield, defect density, lithographic resolution, leakage, interconnect — is now binding, and is the next coordinated push aimed at relaxing it? That reframes a sprawling roadmap into a moving sequence of binding constraints, and reframes the slowdown not as the curve failing but as the industry reaching limits where the old coordinated shrink no longer relaxes the constraint that matters.

Manages Complexity

Forecasting the trajectory of semiconductor capability would otherwise require holding an entire interlocking industry in view at once: process-node generations, photolithographic resolution, defect-density and yield management, mask-cost escalation, the readiness of EDA tools and design libraries, the lockstep advance of lithography-equipment, photoresist, and materials suppliers, and the die-size economics that set what is buildable at acceptable yield. Moore's law compresses that whole apparatus into a single coordinating cadence — transistor count per economically optimal die doubling on a roughly two-year schedule — that the industry does not merely observe but codifies into a roadmap and resources against. The strategist plans not by modeling the full stack each generation but by treating the cadence as the shared expectation all the complementary inputs are timed to meet, so the qualitative question "will the transistor budget I need be there?" is read off the roadmap rather than re-derived from lithography physics. The endogenous, self-fulfilling character of the cadence is exactly what licenses this: because the forecast shapes the coordinated investment that produces the outcome, the single number stands in for the coordination it organizes.

Two pieces of branch structure ride on the compression. First, the law fixes what is doubling — transistor density per die, not clock speed, energy per operation, or delivered performance — so the analyst keeps the count axis separate from the others a chip improves along, and reads the post-2005 history correctly: when Dennard scaling broke, frequency stalled and progress migrated to parallelism, specialization, 3D stacking, and gate-all-around geometries while raw density slowed, which the count metric renders as a change of axis rather than the end of progress. The "More than Moore" transition is thus a labeled branch, not a failure of the curve. Second, the per-generation structure reduces the sprawling roadmap to a moving sequence of single binding constraints: at each node the analyst asks which one constraint — yield, defect density, lithographic resolution, leakage, interconnect — is now binding, and whether the next coordinated push is aimed at relaxing it. The qualitative state of the industry is read off the identity of the current binding constraint and whether the cadence's coordinated investment still relaxes it; when the old coordinated shrink no longer touches the constraint that matters, the slowdown reads as a reached limit rather than the curve mysteriously failing. A whole-industry forecasting problem reduces to one cadence number, a fixed count axis held apart from the rest, and a single-binding-constraint reading per generation.

Abstract Reasoning

Moore's law licenses reasoning moves that turn on its distinctive endogenous character — the cadence is not merely observed but built to — and on holding the transistor-count axis apart from the other axes a chip improves along.

Cadence-as-plan forecasting (predictive/interventionist): The characteristic move treats the doubling not as an exogenous physical gift to wait for but as a coordination device the industry resources, and plans against it. A chip designer reasons FROM "the roadmap promises ~2× transistors in two years, ~4× in four" TO concrete architectural commitments affordable only at those budgets — out-of-order execution, deeper pipelines, larger caches, branch predictors, SIMD units — confident the budget will materialize because the complementary inputs (EDA tools, design libraries, lithography equipment, photoresists, fab capacity) are all timed to the same cadence. The move runs forward from a node's expected transistor budget to what becomes buildable, letting an architect commit to a design before the silicon exists; the intervention reading is that the cadence is a plan to be invested in, not a forecast to be passively awaited.

Self-fulfilling-roadmap reasoning (diagnostic): A distinctive move diagnoses why the trend held for decades where uncoordinated exponentials stall, by reading the causal arrow as endogenous: the forecast, once codified into the ITRS/IRDS roadmap, shaped the coordinated investment that produced the outcome. The engineer reasons FROM "all the complementary inputs arrived together on schedule" TO "the cadence was manufactured by coordinated investment against a shared expectation," not "the technology happened to permit it." This separates two readings — exogenous capability improvement versus endogenous coordinated production — and the move matters because it predicts the cadence is sustainable only as long as the coordination holds, and explains the durability that bare physics would not.

Count-axis discrimination (diagnostic/boundary-drawing): The move holds fixed what is doubling — transistor density per economically optimal die — and refuses to read clock speed, energy per operation, or delivered performance off the same curve. This discrimination becomes decisive at the 2005 Dennard breakdown: frequency stalled and progress migrated to parallelism, specialization, 3D stacking, and gate-all-around geometries while raw density slowed, and the move renders that history as a change of axis rather than the end of progress. Reasoning runs FROM an observed slowdown on one axis TO the question "which axis, and is progress continuing on another?" — so the "More than Moore" era reads as a labeled branch (progress on new axes) rather than the curve failing. Conflating the axes would misdiagnose an axis-shift as collapse.

Per-generation binding-constraint diagnosis (diagnostic/interventionist): The per-generation structure licenses a recurring move: at each node, identify which single constraint — yield, defect density, lithographic resolution, leakage, interconnect — is now binding, and ask whether the next coordinated push is aimed at relaxing it. The reasoning runs FROM the current node's symptoms TO the one binding constraint, and FROM that constraint TO where coordinated investment must target next. This reframes a sprawling roadmap as a moving sequence of single binding constraints, and reframes a slowdown precisely: when the old coordinated shrink no longer relaxes the constraint that matters, the stall reads as a reached limit rather than the curve mysteriously failing.

Extrapolation-boundary discipline (boundary-drawing): A characteristic move marks where the cadence can and cannot be carried. Because the productive mechanism is semiconductor-specific — lithographic shrink, fab capacity, ITRS coordination — extrapolating the doubling to a different substrate is licensed only insofar as that substrate shares the underlying mechanics (industry coordination plus a learning curve). The move reasons FROM "does this other technology have the coordination-plus-learning machinery?" TO whether a "Moore's law for X" claim carries real shared mechanics or is mere analogy — so genome-sequencing cost following a Moore-like curve "until it didn't," and solar PV cost following a learning-driven rather than lithography-driven curve, are read as warnings that the cadence is not a free law of technology but a substrate-bound product of a specific coordinated apparatus.

Knowledge Transfer

Within the semiconductor industry — its home domain — Moore's law transfers as a working coordination device across the entire supply chain, and the transfer is mechanistic because the cadence is not merely observed but built to: chip designers, lithography- and materials-suppliers (ASML, Applied Materials, Lam Research), photoresist and EDA-tool vendors, and fab operators all time their investments to the same roadmap, so the complementary inputs for each node arrive together. The cadence-as-plan forecast, the self-fulfilling-roadmap diagnosis, the count-axis discrimination, and the per-generation binding-constraint reading carry without translation across these subfields because they all share the one apparatus — process-node shrink, ITRS/IRDS coordination, yield-and-die economics — that the law operationalizes. The vocabulary travels intact within this range because the referent (transistor count per economically optimal die, advanced by coordinated investment against a shared expectation) does not change from designer to equipment-maker to fab.

Into the broader computing economy the law propagates one step further, but as a cadence expectation borrowed by sibling laws rather than as the same mechanism transferring whole. The adjacent eponymous doubling-laws — Koomey's law (energy efficiency per operation, itself a Dennard-era consequence of Moore scaling), Kryder's law (hard-disk areal density), Cooper's law (cellular spectrum efficiency), Edholm's law (telecom bandwidth) — are each their own substrate-specific regularity invoked as "Moore's-law-like," and they are best read as a cluster of related domain-specific entries, not as Moore's law reaching into new fields. What they share with it is the abstract shape, not its semiconductor machinery.

Beyond computing the transfer is genuinely mixed, and the two cases must be kept apart. Where "Moore's law for X" is invoked for genome-sequencing cost (which tracked a Moore-like curve "until it didn't") or a software-performance extrapolation, it is usually heuristic analogy: it signals an expectation of exponential cost-decline or capability-gain while renaming the components and dropping the lithography-and-coordination mechanism that gave the original its decades of durability, so the curve carries no commitment about why it should continue. But there is a real shared abstract mechanism underneath the cases where the analogy carries weight — solar PV (Swanson's law) and lithium-ion battery cost curves, and the post-2007 industry-coordinated genome-sequencing declines — and that mechanism is industry-coordinated learning-curve doubling: an industry agrees on an investment cadence, the cadence becomes a forecast, the forecast becomes a roadmap participants build to, and the coordinated investment helps cause the trajectory it ostensibly describes. That pattern really does recur across these substrates as co-instances, but it travels as the more general primes Moore's law instantiates — exponentiation (the curve's mathematical shape), learning_curve (Wright's-law cost decline with cumulative production), coordination_problem_and_equilibrium_selection (the mechanism by which an industry agrees on a roadmap, of which the ITRS process is a success), and self_fulfilling_prophecy (the forecast-shapes-investment-shapes-outcome loop that explains the durability bare physics would not) — not as "Moore's law" itself. The home-bound cargo is exactly the semiconductor apparatus: transistors, photolithographic shrink, fab capacity, the specific binding-constraint sequence (yield, defect density, lithographic resolution, leakage, interconnect), and the ITRS/IRDS coordination structure, none of which survives extraction. So the honest instruction is that when the cross-domain lesson is wanted — the industry-coordination-as-cause-of-the-trajectory dynamic — it should be drawn from learning_curve, coordination_problem_and_equilibrium_selection, self_fulfilling_prophecy, and exponentiation, which transfer as mechanism; "Moore's law," as named, is the canonical semiconductor instance of that conjunction, and extrapolating its specific cadence to another substrate is licensed only insofar as that substrate independently has the coordination-plus-learning machinery. (See Structural Core vs. Domain Accent.)

Examples

Canonical

Gordon Moore's 1965 Electronics article, "Cramming More Components onto Integrated Circuits," observed that the number of components on a minimum-cost integrated circuit had been doubling roughly every year and projected the trend forward a decade. In his 1975 IEDM paper he revised the cadence to a doubling roughly every two years once yield and die-cost economics were better understood. The regularity was subsequently institutionalized: the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS, running 1992–2016) turned the cadence into a shared plan that timed the investments of chip designers, lithography-equipment makers, photoresist and EDA-tool vendors, and fabs so the complementary inputs for each new process node arrived together. The forecast shaped the coordinated investment that produced the outcome it described.

Mapped back: The ~2-year component doubling is the count cadence; photolithographic feature shrink is the lithographic mechanism behind it. The ITRS is the industry roadmap that converts the observation into a plan participants resource against, and the timed advance of tools, resists, and equipment is the complementary inputs. That a codified forecast helped cause the trajectory is the self-fulfilling loop — the durability bare physics would not explain.

Applied / In Practice

The breakdown of Dennard scaling around 2005 is the roadmap's binding-constraint logic in action. As feature sizes fell below roughly 100 nm, leakage currents made further proportional voltage reduction impractical, so power density stopped holding constant — denser chips would now also be hotter chips. Clock frequencies, which had climbed for decades, stalled near a few gigahertz. Rather than the transistor budget failing, the count cadence kept rising while the industry pivoted the budget onto new axes: multi-core parallelism, specialized accelerators (GPUs, later TPUs and NPUs), 3D stacking of SRAM over logic, gate-all-around transistor geometries, and advanced packaging — the "More than Moore" era. Progress migrated to axes the old coordinated shrink could still advance.

Mapped back: Leakage-limited voltage at sub-100 nm nodes is the per-generation binding constraint that turned binding once Dennard scaling broke. The stalled frequency with still-growing transistor count shows why the analyst holds the count cadence apart from clock speed. The pivot to parallelism, specialization, and 3D stacking is the axis-shift / saturation tail — a change of axis, read correctly as continued progress rather than the curve collapsing.

Structural Tensions

T1: Empirical observation versus coordination device (a fact to forecast or a plan to resource). Moore's law reads two ways that pull in opposite directions. As an exogenous regularity, the doubling is something the technology permits and the analyst waits for and forecasts. As an endogenous roadmap — codified into ITRS/IRDS — it is something the industry's own coordinated investment produces: chip designers, lithography and materials suppliers, EDA vendors, and fabs all build to a shared expectation so each node's complementary inputs arrive together. The two readings are not interchangeable: the first treats the cadence as a free gift, the second as a resourced commitment. Reading a manufactured coordination outcome as a law of technology invites complacent extrapolation; reading a genuine physical envelope as mere coordination overstates what investment can force. The name "law" tilts toward the exogenous reading the mechanism contradicts. Diagnostic: Is the cadence here being treated as a physical trajectory to await, or as a coordination outcome that only continues if the industry keeps resourcing it?

T2: Self-fulfilling durability versus coordination-dependent fragility (the source of its strength is the source of its stall). The endogenous, self-fulfilling character is exactly what explains a durability bare physics would not — uncoordinated exponentials stall, and this one held for decades because the forecast shaped the investment that produced the outcome. But that same dependence is the vulnerability: the cadence is sustainable only as long as the coordination keeps relaxing whatever constraint is currently binding, so when the old coordinated shrink no longer touches the binding constraint (leakage, then the limits of planar CMOS), the self-fulfilling loop cannot rescue it. The very mechanism that made the trend robust also makes it contingent on continued coordination and a still-relaxable constraint — a self-fulfilling prophecy can become a self-limiting one. Diagnostic: Is the current cadence holding because coordinated investment is still relaxing the binding constraint, or is the roadmap being resourced against a constraint the old shrink can no longer move?

T3: The count axis versus the axes users experience (what doubles is not what is felt). Holding transistor density per die distinct from clock speed, energy per operation, and delivered performance is what makes the post-2005 history legible: frequency stalled while the count kept climbing, and "More than Moore" reads as a change of axis rather than collapse. But the discipline cuts both ways. The metric that keeps doubling is not the one an end user or software workload directly experiences, so a strictly honest "Moore's law is alive" (density still rising) can coexist with a stalled user-relevant trajectory (single-thread performance flat, hard-to-parallelize workloads unhelped). The count axis stays clean at the risk of becoming a hollow tracker — technically advancing while the capability people actually wanted plateaus. Diagnostic: Is progress being claimed on the transistor-count axis while the axis the workload actually depends on — frequency, single-thread performance, energy per useful operation — has stalled?

T4: Cadence-as-plan enabling forward commitment versus stranded bets when the budget slips (designing to silicon that does not exist). The roadmap's great gift is that an architect can commit to transistor-budget-dependent designs — deeper pipelines, larger caches, SIMD units — before the silicon exists, confident the budget will materialize because all complementary inputs are timed to the same cadence. That forward commitment is only rational because the cadence is a coordinated plan rather than a hope. But the same commitment is exposed precisely when the cadence slips: a design resourced against a node's expected budget is stranded if yield, defect density, or the binding constraint delays that budget, and the deeper the design leans on the promised transistors, the costlier the miss. The roadmap converts a forecast into a plan worth betting on, and betting on a plan means bearing the cost when coordination falters. Diagnostic: Is this design's dependence on a future node's transistor budget backed by a cadence still demonstrably on schedule, or is it a bet exposed to a constraint that may not be relaxed in time?

T5: Real shared mechanism versus heuristic analogy ("Moore's law for X"). The cadence is invoked for genome sequencing, solar PV, batteries, storage, and bandwidth — and these split into two kinds that look identical from the shape alone. Some (solar PV's Swanson's law, post-2007 sequencing, battery cost curves) genuinely share the underlying machinery — industry-coordinated learning-curve doubling, where a cadence becomes a forecast becomes a roadmap participants build to — and the extrapolation carries real commitment about why it should continue. Others borrow only the exponential shape while dropping the coordination-plus-learning mechanism, so the curve carries no reason to persist and "tracked a Moore-like curve until it didn't." The tension is that the name lends borrowed durability to curves that may have none: the phrase signals inevitability the specific substrate has not earned. Diagnostic: Does this "Moore's law for X" curve independently possess the coordination-plus-learning machinery, or is it an exponential shape wearing a borrowed name with no mechanism to sustain it?

T6: Autonomy versus reduction (the named semiconductor cadence or the coordinated-learning-curve dynamic it instantiates). "Moore's law" is a specific, canonically named regularity with proprietary cargo — transistors, photolithographic shrink, fab capacity, the ITRS/IRDS coordination structure, and the particular binding-constraint sequence (yield, defect density, lithographic resolution, leakage, interconnect). None of that survives extraction to another substrate. What genuinely travels cross-domain is the conjunction of more-general primes it instantiates: exponentiation (the curve's shape), learning_curve (cost decline with cumulative production), coordination_problem_and_equilibrium_selection (an industry agreeing on a roadmap), and self_fulfilling_prophecy (forecast shaping investment shaping outcome). The tension is between a standalone eponymous law that organized an entire industry and the recognition that its portable lesson — industry coordination as cause of the trajectory — belongs to those parents. Diagnostic: Resolve toward learning_curve / coordination_problem / self_fulfilling_prophecy / exponentiation when carrying the dynamic to another substrate; toward the named Moore's law when reasoning about the semiconductor roadmap and its specific binding constraints in situ.

Structural–Framed Character

Moore's law sits at the framed-leaning position on the structural–framed spectrum — not a verdict-laden fallacy label, but a regularity so thoroughly constituted by a human coordinating practice that it cannot be read as substrate-neutral form. The criteria split, and the split is instructive. On evaluative_weight it patterns structural: "Moore's law" convicts nothing and praises nothing — it names a cadence, not a defect or a virtue, the way "feedback" names a neutral mechanism rather than rendering a finding. That single neutral mark is what keeps it off the framed pole. But the remaining four all point framed. Human_practice_bound is high in the strong sense: the cadence is not a fact the industry merely observes but one its own coordinated investment produces — strip away the chip designers, lithography and materials suppliers, EDA vendors, and fabs building to a shared ITRS/IRDS roadmap, and there is no doubling left standing, because the forecast that shaped the investment that produced the outcome has nothing to run on. Institutional_origin is equally pronounced: the entry is an eponymous law codified into a specific coordination device (ITRS 1992–2016, then IRDS), its "law" status an artifact of an industry roadmap rather than a constant of nature — the very reason its own What It Is Not leads with "not a law of physics." On vocab_travels it scores low: transistors, photolithographic shrink, process nodes, fab capacity, and the binding-constraint sequence (yield, defect density, leakage, interconnect) are all pinned to the semiconductor substrate and float nowhere free of it. And on import_vs_recognize it patterns as import-by-analogy: "Moore's law for X" invoked for genome cost or solar PV borrows the exponential shape while dropping the lithography-and-coordination machinery, so what crosses is metaphor, not the named mechanism.

The portable structural skeleton is a self-fulfilling, industry-coordinated learning curve — a shared expectation codified into a roadmap that participants resource against, so the coordinated investment helps cause the very trajectory it forecasts. That skeleton is genuinely substrate-spanning and recurs as mechanism across solar-PV, battery-cost, and post-2007 sequencing curves, which is what tempts a structural reading. But it does not pull Moore's law toward the structural end, because that skeleton is precisely what Moore's law instantiates from its umbrella primes — self_fulfilling_prophecy, learning_curve, coordination_problem_and_equilibrium_selection, and exponentiation — not what makes "Moore's law" itself travel: the cross-domain reach belongs to those parents, while the eponymous law's distinctive content, the whole semiconductor apparatus, is exactly the part that stays home. Its character: a normatively neutral but practice-constituted, institution-born industry cadence whose durability is a coordinated human artifact, structural only in the self-fulfilling-learning-curve skeleton it borrows from its parents and dresses in semiconductor vocabulary.

Structural Core vs. Domain Accent

This is the section that settles why Moore's law is a domain-specific abstraction rather than a prime — and it carries the case for its domain-specificity in the same breath, since the entry has no separate section for that.

What is skeletal (could lift toward a cross-domain prime). Strip the silicon and a thin relational structure remains: an industry converges on an investment cadence, the cadence becomes a forecast, the forecast is codified into a roadmap participants resource against, and the coordinated investment helps cause the very trajectory it claims merely to describe — an improvement path held on schedule by the shared expectation itself. Four abstract pieces travel: an exponential improvement curve, a cost-decline that tracks cumulative committed effort rather than calendar time, a coordination act by which many independent actors agree on one timetable, and a forecast that is self-confirming because acting on it produces the outcome. That skeleton is genuinely substrate-portable, which is exactly why it recurs as the parent primes the entry instantiates — exponentiation (the curve's shape), learning_curve (cost decline with cumulative output), coordination_problem_and_equilibrium_selection (the industry agreeing on a roadmap), and self_fulfilling_prophecy (the forecast-shapes-investment-shapes-outcome loop) — but it is the core Moore's law shares, not what makes it distinctive.

What is domain-bound. Everything that makes the cadence Moore's law in particular is semiconductor furniture that does not survive extraction: transistor count per economically optimal die; photolithographic feature shrink and expanding viable die size; process nodes, fab capacity, mask economics, and defect-density-and-yield management; the ITRS/IRDS coordination apparatus; Dennard scaling and its ~2005 breakdown; the specific per-generation binding-constraint sequence (yield, defect density, lithographic resolution, leakage, interconnect); and the "More than Moore" axis-shift to multi-core parallelism, specialization, 3D stacking, and gate-all-around geometries. These are the worked vocabulary, the instruments, and the empirical history the field actually studies. The decisive test: remove the lithography-and-coordination machinery and "Moore's law" is no longer a durable law of anything — it collapses to a bare exponential, a curve with no account of why it should continue, which is precisely what "Moore's law for X" becomes when the phrase is borrowed elsewhere.

Why this does not clear the prime bar. A prime is a relational structure whose vocabulary travels and whose cross-domain transfer is recognition of the same mechanism, not analogy. Moore's law's transfer is bimodal. Within the semiconductor supply chain it moves intact — chip designers, lithography and materials suppliers, EDA vendors, and fabs read the cadence-as-plan forecast, the self-fulfilling-roadmap diagnosis, and the binding-constraint reading unchanged, because the referent (transistor count advanced by coordinated investment against a shared expectation) does not change from designer to fab. Beyond it, transfer splits: for genome-sequencing cost or a software extrapolation the phrase is bare analogy, borrowing the exponential shape while dropping the coordination-plus-learning mechanism; and where the analogy does carry weight — solar-PV (Swanson's law), battery cost, post-2007 sequencing — what actually recurs is industry-coordinated learning-curve doubling, which travels as the parent primes, not as "Moore's law." Here the skeleton is genuinely doubled — indeed quadrupled — and honestly so: the entry names four distinct parents because the cadence's durability is the conjunction of an exponential shape, a learning curve, a coordination success, and a self-fulfilling forecast, no one of which alone explains it. So when the cross-domain lesson is wanted — industry coordination as cause of the trajectory — it is already carried, in more general form, by learning_curve, coordination_problem_and_equilibrium_selection, self_fulfilling_prophecy, and exponentiation. The cross-domain reach belongs to those parents; "Moore's law," as named, carries the semiconductor apparatus that should stay home.

Relationships to Other Abstractions

Local relationship map for Moore's lawParents appear above the current abstraction, mutual partners to the right, and children below. Node labels state whether each abstraction is prime or domain-specific; colors identify relation types.Moore's lawDOMAINPrime abstraction: Exponentiation — is a decomposition ofExponentiationPRIMEDomain-specific abstraction: Bell's Law of Computer Classes — presupposesBell's Law ofComputer ClassesDOMAIN

Current abstraction Moore's law Domain-specific

Parents (1) — more general patterns this builds on

  • Moore's law is a decomposition of Exponentiation Prime

    Moore's Law decomposes to Exponentiation because its portable quantitative skeleton is repeated doubling at an approximately fixed interval.

Children (1) — more specific cases that build on this

  • Bell's Law of Computer Classes Domain-specific presupposes Moore's law

    Bell's recurring class formation presupposes the sustained semiconductor scaling described by Moore's Law, which supplies the cost-and-capability trajectory that repeatedly crosses new feasibility thresholds.

Hierarchy paths (2) — routes to 2 parentless roots

Not to Be Confused With

  • Dennard scaling. The complementary semiconductor claim that voltage and current fall proportionally with feature size so power density stays roughly constant — what kept denser chips from being hotter chips. Moore's law is the transistor-count trajectory; Dennard scaling is the power trajectory that rode alongside it and broke down around 2005 while the count doubling continued for years. Collapsing the two erases exactly the post-2005 divergence — more transistors, but power-constrained — that defines the modern history. Tell: is the claim about how many transistors a die holds (Moore) or about whether the denser die stays within its power budget (Dennard)?

  • Rock's law (Moore's second law). The observation that the capital cost of building a leading-edge semiconductor fab roughly doubles every few years — an escalating-cost curve, not an escalating-capability one. It is the economic counter-pressure on Moore's law (rising fab cost is one of the forces that eventually strains the cadence), not another version of it. Tell: Moore's law tracks a capability that grows; Rock's law tracks a fab price that grows and works against the cadence's continuation.

  • The sibling doubling-laws (Koomey's, Kryder's, Cooper's, Edholm's). Each is its own substrate-specific exponential regularity — energy efficiency per operation, hard-disk areal density, cellular spectrum efficiency, telecom bandwidth — invoked as "Moore's-law-like." They share the cadence shape but each has its own machinery and none is produced by lithographic shrink plus ITRS coordination. Tell: they are best read as a cluster of related domain-specific entries, not as Moore's law reaching into new fields — the name travels, the semiconductor apparatus does not.

  • The learning curve (Wright's / Swanson's law). The empirical decline of unit cost with cumulative production — the experience curve behind solar-PV and battery cost. It is one of Moore's law's parent mechanisms, but it indexes cost to how much has been made, whereas Moore's law indexes density to calendar time. Where a "Moore's law for X" curve genuinely carries weight (solar PV, batteries, post-2007 sequencing), what actually recurs is this learning-curve dynamic, not the semiconductor cadence. Tell: is the improvement clocked by elapsed years (Moore-shaped) or by accumulated output (learning curve)?

  • "Moore's law for X" analogies. Extensions of the phrase to genome-sequencing cost, software performance, or any exponential-looking trend. These usually borrow only the exponential shape while dropping the lithography-and-coordination mechanism that gave the original its durability, so the curve carries no commitment about why it should continue — genome-sequencing cost tracked a Moore-like curve "until it didn't." Tell: does the borrowed curve independently possess the coordination-plus-learning machinery, or is it an exponential wearing a borrowed name with no mechanism to sustain it?

  • The parent primes it instantiates (exponentiation, learning_curve, coordination_problem_and_equilibrium_selection, self_fulfilling_prophecy). The substrate-neutral patterns whose conjunction Moore's law is the canonical semiconductor instance of — the curve's mathematical shape, cost-decline with cumulative output, an industry agreeing on a roadmap, and a forecast that shapes the investment that produces its own outcome. Moore's law is the named instance, not the general pattern; the cross-domain lesson (industry coordination as cause of the trajectory) belongs to these four. Tell: strip away the transistors, the photolithography, and the ITRS roadmap and what remains is bare industry-coordinated learning-curve doubling — at which point you are using these parents, not Moore's law. (Treated fully in earlier sections.)

Neighborhood in Abstraction Space

Moore's law sits in a sparse region of the domain-specific corpus (75th percentile for distinctiveness): few abstractions share its structure, so a faithful description tends to retrieve it precisely.

Family — Unclustered & Miscellaneous (309 abstractions)

Nearest neighbors

Computed from structural-signature embeddings · 2026-07-12