Register–memory architecture¶
Register–memory architecture denotes a computer instruction set architecture within instruction-set architecture.
Core Idea¶
A register–memory architecture is an instruction-set design in which an arithmetic or logical instruction may take at least one operand directly from memory instead of requiring every operand to be loaded into processor registers first. A typical two-operand addition can combine a register value with a memory value in one architecturally visible instruction. Some designs also permit the result to be written directly to memory; the broader register-plus-memory form permits source and destination operands in either registers or memory for the supported operations.
Scope of Application¶
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Instruction-set classification. It distinguishes operations that may directly combine a register operand with a memory operand from load–store forms requiring explicit loads and stores.
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Compiler instruction selection. Back ends choose legal addressing modes and decide when folding a memory access into an operation reduces or increases work.
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Code-density analysis. Encoding an address within an arithmetic or logical instruction can reduce instruction count while increasing instruction complexity.
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ISA-family comparison. x86, PDP-11, VAX, and similar designs can be compared only at the level of specific instruction families, data types, and operand permissions.
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Decode and architectural analysis. Variable operand locations shape the visible instruction format and exception contract.
Clarity¶
Register–memory architecture makes the programmer-visible operand rule explicit: at least some computational instructions may name memory directly. This avoids conflating instruction syntax with an implementation's internal micro-operations and separates one-memory-operand designs from both strict load–store machines and unrestricted memory-to-memory designs. Once the term is fixed, an architect can ask which operations, addressing modes, and destination forms admit memory operands, and what code-density, decoding, and latency consequences follow from.
Manages Complexity¶
Register–memory architecture compresses a large instruction set into a small operand-location signature. An analyst tracks which operations admit a memory source, whether memory may be the destination, how many memory operands are allowed, and which addressing modes apply. Those permissions predict instruction count, code density, decode variability, memory-dependency exposure, and likely internal decomposition without cataloging every program.
Abstract Reasoning¶
Classification move. From the legal operand combinations of arithmetic instructions, classify an ISA as load–store, register–memory, or a broader memory-to-memory design. Code-generation move. From permission for one memory operand, infer that some explicit loads can be fused into computation, while checking destination and addressing restrictions before counting saved instructions. Cost move. From more varied operand forms, predict denser code but greater decode and latency variability, not automatic speedup. Layer-boundary move.
Knowledge Transfer¶
Within the home domain. Register–memory architecture transfers across instruction-set analysis, compiler code generation, processor design, and emulation where arithmetic or logical instructions combine at least one register operand with a directly addressed memory operand. Operand forms, addressing modes, visible destinations, code density, decoding, and micro-operation splitting retain technical roles. Beyond the home domain (C — architecture classification). It applies literally only to instruction sets exposing that operand contract; general memory hierarchies and load–store machines are contrasting designs.
Neighborhood in Abstraction Space¶
Register–memory architecture sits in a sparse region of the domain-specific corpus (71st percentile for distinctiveness): few abstractions share its structure, so a faithful description tends to retrieve it precisely.
Family — Processor Architecture & Instruction Sets (8 abstractions)
Nearest neighbors
- Instruction Set Architecture — 0.87
- Processor Design — 0.84
- Reduced Instruction Set Computer — 0.84
- Bit-Serial Architecture — 0.84
- Computer architecture — 0.82
Computed from structural-signature embeddings · 2026-10-08