Uniform Memory Access¶
A shared-memory processor domain with no local-versus-remote main-memory placement tier.
Core Idea¶
Uniform memory access (UMA) is a shared-memory processor architecture with no privileged near-versus-far main-memory placement tier inside a declared domain and active mode. Controller interleaving or a global route can realize this relation. Caches, contention and queues can still change measured time; UMA does not promise identical latency for every request.[ref-b5f66acb77ad][ref-ad92acc5697c]
Scope of Application¶
Apply UMA to an explicitly configured shared-memory processor domain, tracing eligible requesters and main-memory placements:
- Controller-interleaved package: Intel's Xeon Scalable Processor Max UMA mode interleaves addresses among memory controllers.[^ref-b5f66acb77ad]
- Multi-board SMP domain: Sun's Starfire sends even same-board memory requests through the global interconnect.[ref-83d21192b124][ref-ad92acc5697c]
These are two unlike hardware settings with the same placement-class diagnostic; their physical routes are different.
Clarity¶
Ask: Is memory shared? Which domain and mode are active? Does any placement get a privileged local route? What was actually measured? Sun Fire E25K has a board-local shortcut and distinct interconnect classes, showing that shared addresses alone do not establish UMA. The internal Invariance concerns architectural placement class, not equal numerical timing.[ref-11a566afd44d][ref-ad92acc5697c]
Manages Complexity¶
Many cores, boards, caches and controllers make locality hard to classify. Track configured domain → eligible memory locations → request routes → placement classes. This keeps a shared-memory label or a crossbar diagram from substituting for the route test. Workload performance still requires separate measurement; E25K's pin-to-pin values are conditional interconnect figures.[ref-b5f66acb77ad][ref-11a566afd44d]
Abstract Reasoning¶
Compare eligible requester–location pairs, then test the same-board case for a local shortcut. Starfire retains the global route; E25K can bypass Fireplane traffic. This contrast separates placement-class invariance from simple shared addressability. Shared Memory is the broader context, while Non-uniform Memory Access names the contrasting tiered arrangement.[ref-ad92acc5697c][ref-11a566afd44d]
Knowledge Transfer¶
The route test transfers from Intel's configured controller-interleaved mode to Starfire's multi-board domain: state the scope, trace paths, and look for a local tier. Their mechanisms do not transfer wholesale. The parent prime Invariance captures the bounded preservation under eligible requester or placement changes; extending the hardware classification to other domains needs fresh evidence.[ref-b5f66acb77ad][ref-83d21192b124][^ref-ad92acc5697c]
Relationships to Other Abstractions¶
Current abstraction Uniform Memory Access Domain-specific
Parents (1) — more general patterns this builds on
-
Uniform Memory Access is part of Invariance Prime
A bounded requester/placement-invariant main-memory access class is the identity-bearing internal property of UMA.
Hierarchy path (1) — routes to 1 parentless root
- Uniform Memory Access → Invariance
Neighborhood in Abstraction Space¶
Uniform Memory Access sits in a sparse region of the domain-specific corpus (98th percentile for distinctiveness): few abstractions share its structure, so a faithful description tends to retrieve it precisely.
Family — Unclustered & Miscellaneous (2721 abstractions)
Nearest neighbors
- Multikernel — 0.78
- Cache-Only Memory Architecture — 0.77
- Mixed Criticality — 0.76
- Memory Management — 0.75
- Segmentation Fault — 0.75
Computed from structural-signature embeddings · 2026-10-17
References¶
[^ref-b5f66acb77ad]: Intel. (2022). "Technical Overview Of The Intel® Xeon® Scalable processor Max Series". https://www.intel.com/content/www/us/en/developer/articles/technical/xeon-scalable-processor-max-series.html. Describes the configured mode in sections "Uniform Memory Access Domain" and "Sub-NUMA Clustering"; this manufacturer article is not a benchmark establishing identical transaction latency.
[^ref-83d21192b124]: Alan Charlesworth et al., "The Starfire SMP interconnect" (1997), Proceedings of the 1997 ACM/IEEE Conference on Supercomputing, pp. 1–20. DOI: 10.1145/509593.509630. Describes the design in §§3 and 5; publisher record and abstract at https://doi.org/10.1145/509593.509630 and full original author text at the third-party mirror https://www.filibeto.org/~aduritz/truetrue/e10000/starfire-interconnect.html. The publisher full PDF was not independently inspected; the decisive same-board path is corroborated by the separate 1998 original below.
[^ref-ad92acc5697c]: Alan Charlesworth, "Starfire: Extending the SMP Envelope" (1998), IEEE Micro 18(1):39–49, DOI 10.1109/40.653032, full original article PDF at an academic host, especially printed p. 41 on same-board memory and board-independent access time. This is a distinct publication from the SC '97 paper.
[^ref-11a566afd44d]: Sun Microsystems, Inc., "Sun Fire E25K/E20K Systems Overview" (2006). https://docs.oracle.com/cd/E19065-01/servers.e25k/817-4136-13/4_Interconnect.html. Describes the system interconnect in Chapter 4, §§4.1–4.5, Tables 4-2 and 4-3; manufacturer part number 817-4136-13. Its listed nanoseconds are calculated pin-to-pin interconnect latency classes under stated conditions, and E25K is a negative case distinct from Starfire.