SIS: A System for Sequential Circuit Synthesis¶
Sentovich, E. M. (1992). SIS: A System for Sequential Circuit Synthesis.
Cited by¶
1 citation across 1 artifact.
Each citation links to the sentence it supports in the citing article.
Domain-specific¶
- Logic Synthesis
- A Verilog expression that selects one of two inputs and a state-transition description that becomes a target netlist are different sources for the same specification-to-realization relation.
This sourceUsed for bounded input/output and sequential-preservation claims; full report was not needed for these claims.
- A Verilog expression that selects one of two inputs and a state-transition description that becomes a target netlist are different sources for the same specification-to-realization relation.
Verification¶
Does it exist? Not checked yet. This entry carries no identifier to resolve. It was extracted from the citation as written in the article, normalized, and deduplicated against the rest of the registry.
Does it back the claim? Not recorded. The single citation of this work carries no recorded support check.
Support is checked per citation rather than per work — the same source can be cited soundly in one article and wrongly in another. Per-citation recording began recently, so a citation with no recorded check is a gap in the record rather than evidence it went unchecked.
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Registry ID ref:19dc0edc1d50 · see in the full table