Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs¶
Schlaak, C., Fakih, M., & Stemmer, R. (2017). Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs.
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- Synchronous Data Flow
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This sourceOriginal complete author-paper HTML inspected; sections 1, 3 and 4, Figure 1, Table 2 and Figure 6 describe Sobel/JPEG SDF applications, shared-memory FIFO channels, static actor order, and seven implementation mappings.
- A firing reads its required input tokens, performs an operation, and writes its output tokens; an actor may fire many times during one graph iteration.
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