A low-overhead coherence solution for multiprocessors with private cache memories

Papamarcos, M. S., & Patel, J. H. (1984). A low-overhead coherence solution for multiprocessors with private cache memories. Proceedings of the 11th Annual International Symposium on Computer Architecture, 348-354.

Type

Conference paper

Intellectual base

Primary research

Year

1984

Pages

348-354

DOI

10.1145/800015.808204

DOI registrant

Association for Computing Machinery

Link

https://doi.org/10.1145/800015.808204

Cited from

systems_cybernetics

Cited by

1 citation across 1 artifact.

Each citation links to the sentence it supports in the citing article.

Primes

• Record-Reality Divergence
  • The cache-coherence invariant is not a metaphor here but the literal subject matter: protocols like MESI exist precisely because every cached copy of an external state requires an invalidation strategy.

    This sourceIntroduces the MESI write-invalidate cache-coherence protocol — the invalidation strategy that keeps each cached copy coherent with the external state it caches.

    SupportedVerified against the work's full text

    Papamarcos and Patel motivate their four-state Invalid/Exclusive/Shared/Modified write-invalidate protocol by the risk that copies of a shared block in private caches diverge.

    “Should the same writeable data block exist in more ... than one cache, it is possible for one processor to modify its local copy independently of the rest”

    Read by an automated reader; not a human review. How support was checked

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