RISC-V Unprivileged ISA Specification¶

RISC-V Unprivileged ISA Specification: Introduction.

Type: Standard
Intellectual base: Reference work
Link: https://docs.riscv.org/reference/isa/v20240411/unpriv/intro.html

Cited by¶

1 citation across 1 artifact.

Domain-specific¶

Processor Design
- The instruction-set architecture (ISA) defines the externally visible contract: operations, registers, data types, addressing, privilege, exceptions, memory behavior, and other state that software may rely on.
  
  Supported in partVerified against the work's full text
  
  The RISC-V spec makes the ISA one component of the wider EEI defining privilege modes, memory attributes, exception handling and instruction behavior.
  
  “the accessibility and attributes of memory and I/O regions, the behavior of all legal instructions executed on each hart (i.e., the ISA is one component of the EEI), and the handling of any interrupts or exceptions raised during execution including environment calls.”
  From the work's full text.
  
  Read by an automated reader; not a human review. How support was checked

Verification¶

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Registry ID ref:5ffda26dd54f · see in the full table