Intel 64 and IA-32 Architectures Software Developer’s Manual, Combined Volumes¶
Intel Corporation. (2026). Intel 64 and IA-32 Architectures Software Developer’s Manual, Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4.
Cited by¶
4 citations across 3 artifacts.
Each citation links to the sentence it supports in the citing article.
Domain-specific¶
- Extended-Precision Floating-Point Format
- Far Pointer
- Dereference must interpret both parts through the target architecture's translation rules.
- By contrast, in x86 protected mode the segment field is a selector for a descriptor whose cached base, limit, type, and privilege attributes participate in translation and checking; treating the selector as a real-mode paragraph number is wrong.
Mechanisms¶
- No-Op Command
- It plays the role the NOP instruction plays in assembly — a placeholder action that advances the sequence without side effects.
This sourceDefines NOP as an instruction-stream placeholder that advances EIP while leaving registers, memory, and flags unchanged.
- It plays the role the NOP instruction plays in assembly — a placeholder action that advances the sequence without side effects.
Verification¶
This reference passed the adversarial substantiation pipeline: it was checked to exist and to support the claim it is attached to. See how references were verified.
Links previously used in the corpus¶
Before the registry existed this work was also linked 3 other ways.
- https://cdrdv2-public.intel.com/874249/253668-090-sdm-vol-3a.pdf ×1
- https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf ×1
- https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ×1
Registry ID ref:6f0a53d3ba8d · see in the full table