Logic Synthesis and Verification Algorithms

Hachtel, G. D., & Somenzi, F. (1996). Logic Synthesis and Verification Algorithms. Kluwer Academic.

Type

Book

Intellectual base

Review or monograph

Year

1996

DOI

10.1007/0-387-31005-3

ISBN

9780387310046

DOI registrant

Springer Nature

Link

https://doi.org/10.1007/0-387-31005-3

Cited from

computer_science

Cited by

2 citations across 2 artifacts.

Each citation links to the sentence it supports in the citing article.

Primes

• Equivalence-Preserving Rewriting
  • Hardware synthesis: equivalent-circuit rewrites under logical equivalence, scored by gate count, depth, or power.

    This sourceStandard reference on logic synthesis: replacing sub-circuits with functionally (logically) equivalent but structurally simpler implementations, optimizing for area, delay, and power — equivalent-circuit rewriting under logical equivalence scored by a cost criterion.

Domain-specific

• Join and meet
  • The entry records a descriptive analytical identity; practical use requires the governing domain's evidence, standards, and safety obligations.

Verification

Does it exist? Confirmed. This work's DOI resolves to a registered record, which fixes its identity. That is all it fixes.

Does it back the claim? Not recorded. Neither this nor any other of the 2 citations of this work carries a recorded support check.

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Registry ID ref:721b5528a54f · see in the full table