A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect¶

C Nicoletta, J. A., Barkin, E., Chao, C., Johnson, B. R., & Lassandro, F. M. (1999). A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect. IEEE.

Type: Unclassified
Intellectual base: Unclassified
Year: 1999
DOI: 10.1109/4.799852
Link: https://doi.org/10.1109/4.799852

Cited by¶

1 citation across 1 artifact.

Domain-specific¶

MERSI protocol
- MERSI tracks each cache line as Modified, Exclusive, Recent or Read-Only, Shared, or Invalid, using bus transactions and snooping rules to preserve a coherent memory view.

Verification¶

This reference passed the adversarial substantiation pipeline: it was checked to exist and to support the claim it is attached to. See how references were verified.

Registry ID ref:9f3dc06be93a · see in the full table