Computer Organization and Design RISC-V Edition

Patterson, D. A., John L. Hennessy, C. O., & Design RISC-V Edition, 2. e. (2021). Computer Organization and Design RISC-V Edition: The Hardware/Software Interface. Morgan Kaufmann.

Type

Book chapter

Intellectual base

Review or monograph

Year

2021

ISBN

9780128203316

Link

https://shop.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3

Cited from

computer_science, linguistics_semiotics, mathematics, philosophy, psychology

Cited by

7 citations across 7 artifacts.

Each citation links to the sentence it supports in the citing article.

Primes

• Basis
  • Statistics and computing — principal-component analysis choosing a data-derived basis along directions of maximal variance, and instruction-set design choosing a minimal sufficient set of operations from which all programs compose.

    This sourceTreats instruction-set design as choosing a minimal sufficient set of operations from which all programs compose.

• Implementation Intention
  • The structural reason an implementation intention works is identical to the reason an interrupt handler reliably runs while a polling loop with manual dispatch does not:

    This sourceInterrupt vectors, the interrupt vector table installed at boot, and hardware dispatch on a matching condition — the register-then-dispatch architecture in silicon.

• Interference and Contention
  • CPU scheduling: Multiple processes competing for CPU cycles on a single core or across shared caches; contention causes context-switching overhead, cache misses, and reduced individual process throughput, as Patterson and Hennessy (2017) document in their treatment of shared-cache and memory-bus contention in multicore architectures.

    This sourceMorgan Kaufmann. Develops the hardware-software interface contract — the instruction-set architecture as a published convention binding chip designers, compiler writers, and operating systems — that sustains forty years of binary compatibility as a worked case of convention-bound symbolic representation inside machines.

• Site
  • In hardware, sockets and bays guarantee, through fixed geometry, that a compatible component can be swapped without redesigning the surrounding system.

    This sourceTreats hardware sockets and bays whose fixed geometry guarantees a compatible component can be swapped without redesigning the surrounding system.

• Symbolic Representation
  • The convention-maintenance mechanism is Intel's published instruction-set architecture, the manufacturers who fabricate compatible chips, and the software ecosystem that depends on the encoding remaining stable, a discipline Patterson and Hennessy (2017) develop as the hardware-software interface contract that supports forty years of binary compatibility.

    This sourceMorgan Kaufmann. Develops the hardware-software interface contract — the instruction-set architecture as a published convention binding chip designers, compiler writers, and operating systems — that sustains forty years of binary compatibility as a worked case of convention-bound symbolic representation inside machines.

Domain-specific

• Flat memory model
  • … model, code and data segment descriptors can be configured with base zero and broad limits so effective offsets correspond to one linear address space before optional paging. to A microcontroller exposes code, RAM, peripherals, and reserved regions in one documented numeric address map. demonstrates that continuity.
• Memory address
  • A memory address is a machine-level reference value interpreted within a declared address space to select a storage location or minimum addressable unit for an instruction, device, or software access.

Verification

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Links previously used in the corpus

Before the registry existed this work was also linked 1 other way.

• https://www.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3 ×1

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