Computer Architecture¶
Hennessy, J. L., & Patterson, D. A. (2019). Computer Architecture: A Quantitative Approach. Morgan Kaufmann.
Cited by¶
5 citations across 5 artifacts.
Each citation links to the sentence it supports in the citing article.
Primes¶
- Loading Dose
- In cache and memory systems, cache warming, prefetching, and buffer pre-population at startup spare the first request the empty-cache penalty.
This sourceCompulsory (cold-start) cache misses and hardware/software prefetching to pre-populate the cache and avoid the empty-cache penalty on first access.
- In cache and memory systems, cache warming, prefetching, and buffer pre-population at startup spare the first request the empty-cache penalty.
- Reserve
- Computing: Memory buffers, free-list headroom, swap space, and CPU headroom — all surpluses held against bursty demand, GC pauses, or peak-load spikes, with Hennessy and Patterson (2019) treating the memory hierarchy itself as a stack of reserves sized against access-time and bandwidth contingencies.
This sourceMorgan Kaufmann. Treats the memory hierarchy — register file, multi-level cache, main memory, swap — as a stack of capacity reserves sized against access-time, bandwidth, and miss-rate contingencies; the canonical computing reference for headroom-as-reserve.
- Computing: Memory buffers, free-list headroom, swap space, and CPU headroom — all surpluses held against bursty demand, GC pauses, or peak-load spikes, with Hennessy and Patterson (2019) treating the memory hierarchy itself as a stack of reserves sized against access-time and bandwidth contingencies.
- Specialization
- Hennessy and Patterson (2019) frame domain-specific architectures as the central response to the end of general-purpose scaling — fixed-function silicon wins decisively on its target workload precisely by surrendering the breadth of a CPU.
This sourceMorgan Kaufmann. Treats the memory hierarchy — register file, multi-level cache, main memory, swap — as a stack of capacity reserves sized against access-time, bandwidth, and miss-rate contingencies; the canonical computing reference for headroom-as-reserve.
- Hennessy and Patterson (2019) frame domain-specific architectures as the central response to the end of general-purpose scaling — fixed-function silicon wins decisively on its target workload precisely by surrendering the breadth of a CPU.
Domain-specific¶
Verification¶
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