Computer Architecture¶
Hennessy, J. L., & Patterson, D. A. (2017). Computer Architecture: A Quantitative Approach. Morgan Kaufmann.
Cited by¶
11 citations across 11 artifacts.
Each citation links to the sentence it supports in the citing article.
Primes¶
- Bottleneck
This sourceMorgan Kaufmann. Standard architecture text quantifying performance bottlenecks across the memory hierarchy and pipeline. Biblio reference.
- Caching
- The cache population mechanism (on-demand miss-driven fetch, prefetch/speculative load, or write-through)
This sourceFormalizes the memory-hierarchy performance model τ_avg = h × τ_f + (1 − h) × τ_s and the cache population mechanisms (miss-driven fetch, prefetch, write-through), the cost structures optimized, and the hit/miss analysis driving cache design.
- The cache population mechanism (on-demand miss-driven fetch, prefetch/speculative load, or write-through)
- Concurrency
- A common failure is choosing the wrong synchronization granularity: locks too coarse (unnecessary blocking) or too fine (excessive synchronization overhead)
This sourceCovers thread-level parallelism, cache coherence, synchronization, and lock contention. SUPPORTS marker 057 (T1: independence vs coordination — choosing lock granularity, coarse vs fine). DOI/link is the publisher page. NOTE: the embedded annotation in the source (about 'principle of locality / memory hierarchy / LRU') is a mismatched carry-over from another prime; for marker 057 the relevant content is the book's multiprocessor-synchronization material, which does support the claim.
- A common failure is choosing the wrong synchronization granularity: locks too coarse (unnecessary blocking) or too fine (excessive synchronization overhead)
- Fast-Path / Slow-Path Architecture
- In CPU architecture, branch prediction plus speculative execution bets on the common-case branch and pays a rollback cost only on misprediction, and cache hierarchies stretch the same pattern across levels.
This sourceStandard reference on branch prediction, speculative execution and rollback, and cache hierarchies as common-case/exception cost asymmetries, supporting the CPU-architecture use and the expected-cost (IPC-versus-flush) reading of speculation.
- In CPU architecture, branch prediction plus speculative execution bets on the common-case branch and pays a rollback cost only on misprediction, and cache hierarchies stretch the same pattern across levels.
- Functional Redundancy (Degeneracy)
- As Hennessy and Patterson (2017) document in Computer Architecture: A Quantitative Approach, redundant mechanisms must be coordinated (voting, failover, load balancing), monitored (for silent failure detection), maintained (at 2×–N× the cost of single-path), and reasoned about (common-mode analyses, dependency mapping, failure-tree analysis); each layer of redundancy adds quantifiable area, power, and verification overhead that the architect must budget against the reliability gain.
This sourceMorgan Kaufmann. Canonical quantitative treatment of dependability and redundancy that budgets coordination, monitoring, area, power, and verification overhead against reliability gain; supports the claim that each layer of redundancy adds quantifiable overhead the architect must budget. (Original annotation described the 'principle of locality / memory hierarchy / LRU' — copied from a different prime; corrected to match the redundancy-overhead claim it actually supports.)
- As Hennessy and Patterson (2017) document in Computer Architecture: A Quantitative Approach, redundant mechanisms must be coordinated (voting, failover, load balancing), monitored (for silent failure detection), maintained (at 2×–N× the cost of single-path), and reasoned about (common-mode analyses, dependency mapping, failure-tree analysis); each layer of redundancy adds quantifiable area, power, and verification overhead that the architect must budget against the reliability gain.
- Interior Lines
- Computing and systems architecture. Cache hierarchies put hot data on interior lines to the processor; content-delivery networks put content on interior lines to users; edge and near-memory computing are interior-lines moves.
This sourceStandard reference for cache hierarchies, locality of reference, eviction/prefetch, and cache thrashing when the working set exceeds capacity.
- Computing and systems architecture. Cache hierarchies put hot data on interior lines to the processor; content-delivery networks put content on interior lines to users; edge and near-memory computing are interior-lines moves.
- Locality Of Reference
- The strength of locality is a measurable quantity, not a binary: a workload can have strong, weak, or no temporal locality, and the same stream can be highly local in space but not in time, or vice versa, which is why the two axes are treated as separable dimensions of a single distributional pattern.
This sourceMorgan Kaufmann. Canonical text on the principle of locality: treats temporal and spatial locality as separable, measurable dimensions that the memory hierarchy, paging, prefetching, and LRU-family replacement policies exploit, while noting locality is a probabilistic/aggregate property with no guarantee on individual or adversarial accesses.
- The strength of locality is a measurable quantity, not a binary: a workload can have strong, weak, or no temporal locality, and the same stream can be highly local in space but not in time, or vice versa, which is why the two axes are treated as separable dimensions of a single distributional pattern.
- Mass
- Computing and systems. Cache-line and locality optimization concentrating memory access in time; batch processing concentrating I/O; GPU execution concentrating compute — each a decisive point in a hardware response curve where threshold effects reward concentration.
This sourceCovers locality, batching, and amortization of fixed launch/overhead costs over concentrated workloads (caches, GPU/SIMD execution) where threshold effects reward concentration.
- Computing and systems. Cache-line and locality optimization concentrating memory access in time; batch processing concentrating I/O; GPU execution concentrating compute — each a decisive point in a hardware response curve where threshold effects reward concentration.
- Record-Reality Divergence
- A processor cache is the prime's namesake and its cleanest formal instance.
This sourceCanonical treatment of processor caches, stale reads, lost updates, and cache coherence as the formal record-versus-reality problem.
- A processor cache is the prime's namesake and its cleanest formal instance.
- Scalability
- The identification of the bottleneck component that most constrains scaling in the chosen dimension
This sourceMorgan Kaufmann. Canonical text on the principle of locality: treats temporal and spatial locality as separable, measurable dimensions that the memory hierarchy, paging, prefetching, and LRU-family replacement policies exploit, while noting locality is a probabilistic/aggregate property with no guarantee on individual or adversarial accesses.
- The identification of the bottleneck component that most constrains scaling in the chosen dimension
- Stratification
- Axis: access latency (and cost per byte).
This sourceMorgan Kaufmann. Canonical text on the principle of locality: treats temporal and spatial locality as separable, measurable dimensions that the memory hierarchy, paging, prefetching, and LRU-family replacement policies exploit, while noting locality is a probabilistic/aggregate property with no guarantee on individual or adversarial accesses.
- Axis: access latency (and cost per byte).
Verification¶
This reference passed the adversarial substantiation pipeline: it was checked to exist and to support the claim it is attached to. See how references were verified.
Links previously used in the corpus¶
Before the registry existed this work was also linked 1 other way.
Registry ID ref:d8ae3041901c · see in the full table