Computer Architecture

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16 domain-specific abstractions whose origin domain is Computer Architecture.

• Address generation unit — A CPU execution unit dedicated to calculating effective memory addresses from base, index, scale and displacement components so memory operations can proceed in parallel with other computation.
• Atmel AVR instruction set — Define the encoded machine operations, register effects, addressing modes, flags, timing, and architectural variants executed by AVR 8-bit microcontrollers.
• Cache coherence — The consistency property and protocol discipline that keep multiple cached copies of shared memory observably compatible.
• Cache hierarchy — A layered memory architecture that places progressively larger and slower caches between processors and backing memory to exploit locality at several scales.
• CPU cache — A small fast processor-local memory that retains copies of recently or predictably useful main-memory blocks to reduce average access cost.
• Firefly (cache coherence protocol) — A three-state write-update cache-coherence protocol that keeps shared cache copies and main memory current on broadcast writes.
• Flat memory model — Expose storage to software as one linearly ordered address space in which an address selects a location without a constitutive segment or bank selector, while allowing paging, protection, caching, or physical translation beneath that programmer-visible contract.
• Instruction pipelining — A processor implementation that divides instruction execution into stages and overlaps different instructions across those stages to increase throughput without requiring each instruction to finish before the next begins.
• Instruction-level parallelism — The degree to which independent machine instructions from one execution stream can overlap or execute simultaneously.
• Memory address — Use a fixed-width value within a declared address space to identify an addressable storage unit, with architecture and translation rules determining which physical location a load or store reaches.
• Memory refresh — Periodically sense and restore charge in every dynamic-memory row before leakage crosses the retention margin, preserving stored bits at a recurring availability and energy cost.
• MERSI protocol — A five-state cache-coherence protocol extending MESI with a Recent or Read-Only state to optimize shared cache-line ownership and response behavior in PowerPC G4 systems.
• Non-uniform memory access — A shared-memory multiprocessor architecture in which access latency and bandwidth depend on which processor or node physically owns the addressed memory.
• SHA instruction set — Processor instruction extensions that accelerate selected round, schedule and Boolean primitives of SHA-family cryptographic hash functions.
• Single instruction, multiple data — A parallel-computing organization in which many processing lanes perform the same instruction simultaneously on different data elements.
• Visual Instruction Set — A family of SPARC V9 SIMD instruction-set extensions that perform parallel media, signal and pixel operations in floating-point register storage.