Cache coherence¶

The consistency property and protocol discipline that keep multiple cached copies of shared memory observably compatible.

Version: v2 · 2026-09-19 · History
Domain-specific #: 3570
Domain group: Applied Sciences & Engineering
Origin domain: Computer Science & Software Engineering
Subdomain: Computer Architecture → Computer Science & Software Engineering

Core Idea¶

Coherence concerns per-location visibility and write serialization rather than the broader ordering of operations across locations supplied by memory consistency, protocols can snoop or use directories and “all copies identical at every instant” is too strong for in-flight transactions.^[1] Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization. The abstraction is therefore identified by a declared carrier, a transformation or constraint over that carrier, and an invariant that tells an analyst whether the named structure is genuinely present.

The load-bearing residual is not the broad topic of computer architecture. It is the domain-specific identity fixed by the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. That residual remains recognizable when examples, notation, scale, or implementation change, but it disappears if the carrier is mistyped, the condition that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit fails, a neighboring object is substituted, or notation and topical resemblance replace the constitutive test. This gives the entry an operational identity rather than merely a historical label.

A useful analysis keeps three layers separate. The constitutive layer says what must be true: the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. The evidential layer asks what observation or proof warrants the claim: type the carrier, state every parameter and convention in the definition, test that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases. The use layer asks what reasoning becomes available once the identity is established: recognizing and comparing instances of Cache coherence, deriving its domain-specific consequences, selecting valid models or methods, and preventing transfer beyond its assumptions. Conflating the layers is the most common source of scope inflation.

How would you explain it like I'm…

No Old Copies Rule

Some friends each have a copy of the same page from a notebook. When one friend changes something on the page, the others have to throw away their old copies before they use the page again, so nobody reads old writing. And everybody sees changes to that page in the same order.

Keeping Memory Copies in Sync

Computers with several brains (cores) often keep their own quick copies of pieces of memory, called caches, so they can work faster. The problem is that if one core changes its copy, the others might still have the old value. Cache coherence is the set of rules and messages the cores use to prevent that. When a core wants to write, it gets to be the owner, and the other copies are marked out of date or updated. That way, all the changes to one spot in memory are seen in one agreed order, and nobody uses an outdated copy when it matters.

Per-Address Cache Coherence

In a multicore processor, each core has private caches holding copies of memory in chunks called cache lines. Cache coherence is the guarantee that, for each individual memory location, writes are serialized into one order that all cores observe, and no core keeps reading a stale copy after the required synchronization. Cores track a state for each cache line, such as whether they own it or share it, and exchange messages to invalidate other copies or update them when a write happens. This can be done by snooping, where every cache watches a shared bus, or by directories that record who holds each line. Coherence is about one location at a time; the broader question of how operations on different locations are ordered is memory consistency, a separate concept. It is also too strong to say all copies are identical at every instant, since messages are in flight and lines pass through transient states.

Cache coherence is the property, and the protocols enforcing it, that ensure per-location visibility and write serialization in shared-memory multiprocessors with private caches. For each memory location, writes are serialized into a single order, and once the required synchronization occurs, stale copies can no longer be read. Protocols track per-line states, stable states describing ownership and sharing plus transient states during transactions, and exchange invalidation or update messages under an ownership and serialization rule. Implementations are either snooping, broadcasting on a shared interconnect, or directory-based, tracking sharers per line for scalability. Coherence is distinct from memory consistency, which governs ordering of operations across different locations. The naive formulation that all copies are identical at every instant is too strong, because in-flight messages and transient states are unavoidable. Design and analysis must make explicit the cache-line granularity, cache hierarchy, invariants, states, policy, mechanism, message races and acknowledgments, and effects such as false sharing, where unrelated variables on one line cause coherence traffic.

Structural Signature¶

Carrier: the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets
Inputs or antecedent state: the exact computer architecture carrier, defining parameters and conventions, boundary conditions, source evidence, comparison cases, and any measurement or proof assumptions needed to evaluate Cache coherence
Constitutive operation: Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization.
Invariant: the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit
Recognition test: type the carrier, state every parameter and convention in the definition, test that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases
Output or consequence: recognizing and comparing instances of Cache coherence, deriving its domain-specific consequences, selecting valid models or methods, and preventing transfer beyond its assumptions
Failure boundary: the carrier is mistyped, the condition that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit fails, a neighboring object is substituted, or notation and topical resemblance replace the constitutive test

What It Is Not¶

It is not the whole field of computer architecture. The field contains many questions and methods that do not instantiate Cache coherence.
It is not its most familiar example. A canonical instance directly demonstrates that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. exhibits the structure, but the example is evidence for the abstraction rather than its definition.
It is not the neighboring catalog concept Memory consistency model. A consistency model orders memory operations as observed by programs across addresses; cache coherence maintains a compatible serialization for each location and is one mechanism supporting a model.
It is not a claim that every boundary case has one uncontested classification. a generalized or degenerate case may change existence, uniqueness, measurement, or naming conventions, so the exact definition of Cache coherence must control the decision
It is not an unrestricted metaphor for any process that seems similar. Outside computer architecture, the vocabulary and validity conditions do not transfer literally.

Scope of Application¶

Cache coherence belongs to computer architecture and is useful where the analyst can specify the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, then evaluate the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. The scope is broad within that domain but bounded by the need for the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. The entry records a descriptive analytical identity; practical use requires the governing domain's evidence, standards, and safety obligations.^[2]

Definition and recognition. Determine whether a proposed instance satisfies the constitutive conditions rather than merely sharing terminology.
Construction or evolution. Track how the exact computer architecture carrier, defining parameters and conventions, boundary conditions, source evidence, comparison cases, and any measurement or proof assumptions needed to evaluate Cache coherence are converted, constrained, or organized by Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization..
Comparison. Compare instances using carrier, parameters, convention, domain, scale, boundary conditions, evidence, exact versus approximate form, and limiting behavior, without treating convenience measures as the definition.
Boundary analysis. Diagnose cases where a generalized or degenerate case may change existence, uniqueness, measurement, or naming conventions, so the exact definition of Cache coherence must control the decision and state which convention or theorem controls the decision.
Downstream reasoning. Use the established identity to support recognizing and comparing instances of Cache coherence, deriving its domain-specific consequences, selecting valid models or methods, and preventing transfer beyond its assumptions while preserving the assumptions under which the inference is valid.

Clarity¶

The abstraction clarifies a crowded vocabulary by making the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit the center of the account. A claim should name the carrier, the governing operation or relation, the applicable assumptions, and the recognition test. A bare label is insufficient because the name Cache coherence can be used for a formal identity, an implementation, or a neighboring result unless carrier and convention are stated. The disciplined statement is: given the exact computer architecture carrier, defining parameters and conventions, boundary conditions, source evidence, comparison cases, and any measurement or proof assumptions needed to evaluate Cache coherence, the structure counts as Cache coherence exactly when the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit.

This format also separates identity from measurement. Empirical, computational, or documentary proxies support recognition only under declared validity and uncertainty assumptions; formal cases require proof rather than measurement. Measurements can be noisy, implementations can approximate, and proofs can use equivalent characterizations; none of those facts licenses changing the object being measured. When reports disagree, first check scope and convention, then data or proof, and only then interpret the disagreement as substantive.

Manages Complexity¶

Without the abstraction, an analyst must reason directly over many local details: the carrier roles, admissibility assumptions, competing conventions, derived invariants, boundary cases, and proof or validation obligations specific to Cache coherence. Cache coherence compresses them into the roles in the structural signature. That compression permits comparison across instances without erasing the variables that determine validity. It also exposes which details may be varied safely and which are constitutive.

The compression has a price. A single label can hide canonical, generalized, restricted, approximate, computational, empirical, and historically variant formulations of Cache coherence. Good use therefore carries a small declaration of assumptions alongside the name. The abstraction manages complexity when it reduces the state space of the question while keeping the failure boundary visible; it mismanages complexity when the label substitutes for that boundary analysis.

Abstract Reasoning¶

Identify the carrier. State what the elements, states, objects, or observations are: the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets. Reject examples whose alleged carrier belongs to a different problem.
Lock the constitutive rule. Express the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit independently of one notation or implementation. This step prevents the canonical example from becoming the definition.
Derive consequences. From the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, infer recognizing and comparing instances of Cache coherence, deriving its domain-specific consequences, selecting valid models or methods, and preventing transfer beyond its assumptions. Record each assumption used so that a later change of setting does not silently preserve an invalid conclusion.
Test adversarial cases. Examine a generalized or degenerate case may change existence, uniqueness, measurement, or naming conventions, so the exact definition of Cache coherence must control the decision and an object that resembles Cache coherence in purpose or vocabulary but does not satisfy its invariant is outside the class. A robust identity explains why the first is convention-sensitive and why the second is outside the class.
Compare and refine. Use carrier, parameters, convention, domain, scale, boundary conditions, evidence, exact versus approximate form, and limiting behavior to compare legitimate instances, and refine the model when discrepancies reflect hidden variation rather than failure of the abstraction itself.

Knowledge Transfer¶

Knowledge transfers strongly among subfields of computer architecture because they reuse the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization., and type the carrier, state every parameter and convention in the definition, test that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases. A theorem, diagnostic, or modeling warning can travel when those roles remain literal. For example, the distinction between constitutive identity and a convenient observable transfers from A canonical instance directly demonstrates that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. to An applied instance preserves the invariant under changed notation, scale, dataset, jurisdiction, or implementation..^[n1]

Transfer outside the home domain is weaker. The skeletal pattern—type the carrier, apply the defining mechanism of Cache coherence, preserve its invariant, and derive only consequences licensed by the stated boundary—may suggest an analogy, but the domain-specific mechanisms, admissible evidence, and consequences do not come along automatically. The safe transfer procedure maps each role explicitly, checks the invariant again, and refuses the name when only a superficial resemblance remains.

Examples¶

Canonical¶

A canonical instance directly demonstrates that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit. The example exposes the carrier and directly tests that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit; changing incidental notation preserves the identity, while removing that condition destroys it. This example is canonical because every role can be inspected: the carrier is the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets; the operative rule is Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization.; the invariant is the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit; and the result supports recognizing and comparing instances of Cache coherence, deriving its domain-specific consequences, selecting valid models or methods, and preventing transfer beyond its assumptions.^[1] Changing incidental notation or scale leaves the structure intact, while removing the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit destroys the classification.

Mapped back: the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets → Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization. → the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit → recognizing and comparing instances of Cache coherence, deriving its domain-specific consequences, selecting valid models or methods, and preventing transfer beyond its assumptions

Applied / In Practice¶

An applied instance preserves the invariant under changed notation, scale, dataset, jurisdiction, or implementation. The applied case qualifies only because the same invariant and boundary test remain literal under changed parameters or implementation. The applied case is not licensed merely by vocabulary. It qualifies because the same recognition test—type the carrier, state every parameter and convention in the definition, test that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases—can be run and because the same failure boundary—the carrier is mistyped, the condition that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit fails, a neighboring object is substituted, or notation and topical resemblance replace the constitutive test—remains meaningful.^[2] The case also shows why practical outputs should report assumptions, resolution, and uncertainty instead of a naked label.

Mapped back: declared instance → recognition test → boundary check → qualified use

Structural Tensions¶

T1: Axiomatic identity vs. operational recognition. The defining conditions may be exact while empirical or computational recognition is approximate. Neither pole can be removed without changing the analytical task. Diagnostic: Can the reviewer state both the exact condition and the evidence used to infer it?
T2: Local roles vs. global consequence. The mechanism is enacted through local relations, but the abstraction is usually valued for a global classification or prediction. Neither pole can be removed without changing the analytical task. Diagnostic: Does the claimed global result actually follow from the declared local conditions?
T3: Ideal form vs. finite representation. Theory states a clean invariant while data structures, measurements, or proofs expose only finite representations. Neither pole can be removed without changing the analytical task. Diagnostic: Would increasing resolution converge toward the same classification?
T4: Canonical convention vs. legitimate variants. A standard formulation supports communication, while variants may preserve the same core under changed assumptions. Neither pole can be removed without changing the analytical task. Diagnostic: Which role is invariant across variants, and which convention-specific conclusion changes?
T5: Compression vs. hidden assumptions. The name compresses a complex argument but can conceal prerequisites. Neither pole can be removed without changing the analytical task. Diagnostic: Can each downstream inference be traced to an explicit assumption?
T6: Autonomous residual vs. reduction to catalog neighbors. The candidate uses broader structures but adds an identity-bearing residual. Neither pole can be removed without changing the analytical task. Diagnostic: After subtracting the proposed parent and named neighbors, does the constitutive residual still support independent diagnostics?

Structural–Framed Character¶

The entry is structurally mixed but domain-framed. Its portable skeleton is type the carrier, apply the defining mechanism of Cache coherence, preserve its invariant, and derive only consequences licensed by the stated boundary. Its identity-bearing terms—Cache coherence, carrier, parameter, invariant, boundary, evidence, model, transformation, and application—derive their meaning from computer architecture and cannot be replaced by generic systems language without losing the tests that distinguish valid from invalid instances.

This mixed character explains why the abstraction is reusable inside the domain yet does not meet the Prime bar. The structure organizes reasoning, but its claims still depend on domain-specific objects, evidence, and intervention semantics.

Structural Core vs. Domain Accent¶

The structural core consists of a carrier, Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization., a recognition invariant, and a consequence. That skeleton may resemble patterns elsewhere, especially type the carrier, apply the defining mechanism of Cache coherence, preserve its invariant, and derive only consequences licensed by the stated boundary. The domain accent is not decorative: Cache coherence, carrier, parameter, invariant, boundary, evidence, model, transformation, and application determine what counts as an admissible carrier, a valid transition, and successful evidence.

The abstraction therefore remains domain-specific. A cross-domain reuse that preserves only words such as 'balance,' 'cut,' 'sequence,' 'loss,' or 'simulation' is metaphor. Literal transfer requires the original role structure and diagnostics, which in this case remain anchored in computer architecture.

This entry is a kind of Coordination.

It remains its own entry because its identity is fixed by the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency.

Relationships to Other Abstractions¶

Current abstraction Cache coherence Domain-specific

Parents (1) — outgoing typed relations

Cache coherence is a kind of Coordination Prime

It remains its own entry because its identity is fixed by the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency.

Hierarchy paths (5) — routes to 4 parentless roots

Cache coherence → is a kind of Coordination → presupposes Concurrency

Show alternative paths (4)

Neighborhood in Abstraction Space¶

Cache coherence sits in a crowded region of the domain-specific corpus (13^th percentile for distinctiveness): several abstractions share nearly its structure, so a description that fits it tends to fit its neighbors too.

Family — Memory Architecture & Address Spaces (25 abstractions)

Nearest neighbors

CPU cache — 0.94
Firefly (cache coherence protocol) — 0.93
Cache hierarchy — 0.93
Scratchpad memory — 0.91
Shared memory — 0.90

Computed from structural-signature embeddings · 2026-10-25

Not to Be Confused With¶

Memory consistency model. A consistency model orders memory operations as observed by programs across addresses; cache coherence maintains a compatible serialization for each location and is one mechanism supporting a model.
One canonical example. An instance demonstrates the structure but does not define the whole abstraction.
Measurement or implementation of Cache coherence. A proxy or realization is evidence for the abstraction, not the abstraction itself.
Generalized Cache coherence. An extension qualifies only when its changed axioms and retained invariant are stated.

Notes¶

[n1] Solihin Yan, 'Fundamentals of parallel multicore architecture'. ↩

References¶

[1] Ami Marowka, 'Advances in Computers', Elsevier, 2010-01-01, doi:10.1016/s0065-2458(10)79002-1. registry ↩a ↩b

[2] Michael E. Thomadakis, 'The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms', Texas A&M University, 2011. registry ↩a ↩b