Cache coherence

The consistency property and protocol discipline that keep multiple cached copies of shared memory observably compatible.

Version

v1 · 2026-09-08 · History

Domain-specific #

3570

Origin domain

computer architecture

Subdomain

computer architecture

Core Idea

Coherence concerns per-location visibility and write serialization rather than the broader ordering of operations across locations supplied by memory consistency, protocols can snoop or use directories and “all copies identical at every instant” is too strong for in-flight transactions. Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization. The abstraction is therefore identified by a declared carrier, a transformation or constraint over that carrier, and an invariant that tells an analyst whether the named structure is genuinely present.

Scope of Application

Cache coherence belongs to computer architecture and is useful where the analyst can specify the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, then evaluate the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit.

Clarity

The abstraction clarifies a crowded vocabulary by making the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit the center of the account. A claim should name the carrier, the governing operation or relation, the applicable assumptions, and the recognition test.

Manages Complexity

Without the abstraction, an analyst must reason directly over many local details: the carrier roles, admissibility assumptions, competing conventions, derived invariants, boundary cases, and proof or validation obligations specific to Cache coherence. Cache coherence compresses them into the roles in the structural signature. That compression permits comparison across instances without erasing the variables that determine validity. It also exposes which details may be varied safely and which are constitutive.

Abstract Reasoning

1. Identify the carrier. State what the elements, states, objects, or observations are: the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets. Reject examples whose alleged carrier belongs to a different problem. 2. Lock the constitutive rule. Express the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit independently of one notation or implementation.

Knowledge Transfer

Knowledge transfers strongly among subfields of computer architecture because they reuse the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization., and type the carrier, state every parameter and convention in the definition, test that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases.

Relationships to Other Abstractions

Current abstraction Cache coherence Domain-specific

Parents (1) — more general patterns this builds on

• Cache coherence is a kind of Coordination Prime

  The proposed strict upward parent is prime:coordination.

Hierarchy paths (5) — routes to 4 parentless roots

• Cache coherence → Coordination → Concurrency

Show alternative paths (4)

Neighborhood in Abstraction Space

Cache coherence sits in a crowded region of the domain-specific corpus (22^nd percentile for distinctiveness): several abstractions share nearly its structure, so a description that fits it tends to fit its neighbors too.

Family — Memory Architecture & Parallel Computing (34 abstractions)

Nearest neighbors

• CPU cache — 0.94
• Firefly (cache coherence protocol) — 0.93
• Cache hierarchy — 0.93
• Scratchpad memory — 0.91
• Shared memory — 0.90

Computed from structural-signature embeddings · 2026-09-08