Cache coherence

The consistency property and protocol discipline that keep multiple cached copies of shared memory observably compatible.

Version

v2 · 2026-09-19 · History

Domain-specific #

3570

Domain group

Applied Sciences & Engineering

Origin domain

Computer Science & Software Engineering

Subdomain

Computer Architecture → Computer Science & Software Engineering

Core Idea

Coherence concerns per-location visibility and write serialization rather than the broader ordering of operations across locations supplied by memory consistency, protocols can snoop or use directories and “all copies identical at every instant” is too strong for in-flight transactions. Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization. The abstraction is therefore identified by a declared carrier, a transformation or constraint over that carrier, and an invariant that tells an analyst whether the named structure is genuinely present.

How would you explain it like I'm…

No Old Copies Rule

Some friends each have a copy of the same page from a notebook. When one friend changes something on the page, the others have to throw away their old copies before they use the page again, so nobody reads old writing. And everybody sees changes to that page in the same order.

Keeping Memory Copies in Sync

Computers with several brains (cores) often keep their own quick copies of pieces of memory, called caches, so they can work faster. The problem is that if one core changes its copy, the others might still have the old value. Cache coherence is the set of rules and messages the cores use to prevent that. When a core wants to write, it gets to be the owner, and the other copies are marked out of date or updated. That way, all the changes to one spot in memory are seen in one agreed order, and nobody uses an outdated copy when it matters.

Per-Address Cache Coherence

In a multicore processor, each core has private caches holding copies of memory in chunks called cache lines. Cache coherence is the guarantee that, for each individual memory location, writes are serialized into one order that all cores observe, and no core keeps reading a stale copy after the required synchronization. Cores track a state for each cache line, such as whether they own it or share it, and exchange messages to invalidate other copies or update them when a write happens. This can be done by snooping, where every cache watches a shared bus, or by directories that record who holds each line. Coherence is about one location at a time; the broader question of how operations on different locations are ordered is memory consistency, a separate concept. It is also too strong to say all copies are identical at every instant, since messages are in flight and lines pass through transient states.

 

Cache coherence is the property, and the protocols enforcing it, that ensure per-location visibility and write serialization in shared-memory multiprocessors with private caches. For each memory location, writes are serialized into a single order, and once the required synchronization occurs, stale copies can no longer be read. Protocols track per-line states, stable states describing ownership and sharing plus transient states during transactions, and exchange invalidation or update messages under an ownership and serialization rule. Implementations are either snooping, broadcasting on a shared interconnect, or directory-based, tracking sharers per line for scalability. Coherence is distinct from memory consistency, which governs ordering of operations across different locations. The naive formulation that all copies are identical at every instant is too strong, because in-flight messages and transient states are unavoidable. Design and analysis must make explicit the cache-line granularity, cache hierarchy, invariants, states, policy, mechanism, message races and acknowledgments, and effects such as false sharing, where unrelated variables on one line cause coherence traffic.

Scope of Application

Cache coherence belongs to computer architecture and is useful where the analyst can specify the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, then evaluate the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit.

Clarity

The abstraction clarifies a crowded vocabulary by making the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit the center of the account. A claim should name the carrier, the governing operation or relation, the applicable assumptions, and the recognition test.

Manages Complexity

Without the abstraction, an analyst must reason directly over many local details: the carrier roles, admissibility assumptions, competing conventions, derived invariants, boundary cases, and proof or validation obligations specific to Cache coherence. Cache coherence compresses them into the roles in the structural signature. That compression permits comparison across instances without erasing the variables that determine validity. It also exposes which details may be varied safely and which are constitutive.

Abstract Reasoning

1. Identify the carrier. State what the elements, states, objects, or observations are: the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets. Reject examples whose alleged carrier belongs to a different problem.
2. Lock the constitutive rule. Express the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit independently of one notation or implementation.

Knowledge Transfer

Knowledge transfers strongly among subfields of computer architecture because they reuse the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, Cores track cache-line states and exchange invalidation or update messages; an ownership and serialization rule ensures writes become visible in a coherent order and stale copies cannot be used after required synchronization., and type the carrier, state every parameter and convention in the definition, test that the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases.

Relationships to Other Abstractions

Current abstraction Cache coherence Domain-specific

Parents (1) — outgoing typed relations

• Cache coherence is a kind of Coordination Prime

  It remains its own entry because its identity is fixed by the shared-memory addresses and cache-line granularity, processors and private or shared caches, read and write operations, coherence invariant and write serialization, stable and transient line states, ownership and sharing, invalidate or update policy, snooping or directory mechanism, messages acknowledgments and races, false sharing and distinction from memory consistency.

Hierarchy paths (5) — routes to 4 parentless roots

• Cache coherence → is a kind of Coordination → presupposes Concurrency

Show alternative paths (4)

Neighborhood in Abstraction Space

Cache coherence sits in a crowded region of the domain-specific corpus (13^th percentile for distinctiveness): several abstractions share nearly its structure, so a description that fits it tends to fit its neighbors too.

Family — Memory Architecture & Address Spaces (25 abstractions)

Nearest neighbors

• CPU cache — 0.94
• Firefly (cache coherence protocol) — 0.93
• Cache hierarchy — 0.93
• Scratchpad memory — 0.91
• Shared memory — 0.90

Computed from structural-signature embeddings · 2026-10-25