Memory Architecture & Address Spaces

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Abstractions about how computer systems organize, access and move data through memory, covering address spaces and translation (virtual memory, virtual address space, memory address), cache structures and coherence protocols (CPU cache, cache hierarchy, Firefly and MERSI protocols), and memory-management techniques like demand paging and buffering.

25 abstractions in this family — domain-specific abstractions that sit near one another in structural-signature space (k-means over structural-signature embeddings). Each is shown with its short description.

• Address space — A namespace defining a set or range of discrete addresses and the entities or storage locations each address can identify under a qualification scheme.
• Background process — A computer process that performs work without occupying the user’s foreground interaction.
• Cache coherence — The consistency property and protocol discipline that keep multiple cached copies of shared memory observably compatible.
• Cache hierarchy — A layered memory architecture that places progressively larger and slower caches between processors and backing memory to exploit locality at several scales.
• CPU cache — A small fast processor-local memory that retains copies of recently or predictably useful main-memory blocks to reduce average access cost.
• Data buffer — A temporary memory region that decouples a data producer and consumer whose transfer sizes, rates or scheduling do not align.
• Data deduplication — A storage or transfer technique that replaces repeated data regions with references to one retained instance while preserving reconstruction of the original logical data.
• Data scrubbing — A background integrity process that periodically reads stored or memory-resident data, detects latent corruption and reconstructs correct content from checksums, error-correcting codes or redundant copies.
• Demand paging — A virtual-memory policy that loads a page into physical memory only after an attempted access faults on that absent page.
• Firefly (cache coherence protocol) — A three-state write-update cache-coherence protocol that keeps shared cache copies and main memory current on broadcast writes.
• Flat memory model — Expose storage to software as one linearly ordered address space in which an address selects a location without a constitutive segment or bank selector, while allowing paging, protection, caching, or physical translation beneath that programmer-visible contract.
• Instruction pipelining — A processor implementation that divides instruction execution into stages and overlaps different instructions across those stages to increase throughput without requiring each instruction to finish before the next begins.
• Memory address — Use a fixed-width value within a declared address space to identify an addressable storage unit, with architecture and translation rules determining which physical location a load or store reaches.
• Memory-bound function — A computation whose elapsed time is limited primarily by memory capacity, bandwidth or latency rather than arithmetic throughput.
• MERSI protocol — A five-state cache-coherence protocol extending MESI with a Recent or Read-Only state to optimize shared cache-line ownership and response behavior in PowerPC G4 systems.
• Non-uniform memory access — A shared-memory multiprocessor architecture in which access latency and bandwidth depend on which processor or node physically owns the addressed memory.
• Process state — A scheduler-relevant lifecycle condition of an operating-system process, such as new, ready, running, blocked, suspended, or terminated, together with permitted transitions.
• Scratchpad memory — A small, fast memory explicitly managed by software or a processing unit for temporary data, unlike a hardware-managed cache that automatically mirrors selected main-memory contents.
• Sequential access — An access mode in which elements are reached in a predetermined order and reaching a later element generally requires traversing earlier positions.
• Single instruction, multiple data — A parallel-computing organization in which many processing lanes perform the same instruction simultaneously on different data elements.
• Unique set size — The portion of a process’s resident memory backed by pages private to that process and therefore expected to be reclaimed if it terminates.
• URL — A Uniform Resource Identifier that identifies a resource through a scheme-specific description of how and where it can be accessed.
• Virtual address space — The process-visible range of virtual memory addresses that an operating system maps, protects and backs independently of the machine's physical-address layout.
• Virtual file system — An operating-system abstraction layer that presents a uniform file and directory interface over multiple concrete local, remote or synthetic file systems.
• Virtual memory — Give each process a protected logical address space by translating virtual addresses to physical storage and managing residency, protection, sharing, and replacement independently of the program's apparent contiguous memory.