Memory Architecture & Parallel Computing

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Abstractions about how computing systems address, buffer, cache, share, and synchronize memory while executing work in parallel. They include memory hierarchies, coherence protocols, dependencies, vector instructions, pipelining, address spaces, deduplication, and parallel algorithms.

34 abstractions in this family — domain-specific abstractions that sit near one another in structural-signature space (k-means over structural-signature embeddings). Each is shown with its short description.

• 2 GB limit — A legacy 32-bit process-address-space boundary in which conventional signed or kernel/user partitioning leaves roughly two gibibytes of directly addressable user virtual memory.
• 26-bit computing — A historical architecture regime using 26-bit-wide addresses or values, notably extending IBM real addressing and embedding ARM's 26-bit program counter with status bits.
• Address generation unit — A CPU execution unit dedicated to calculating effective memory addresses from base, index, scale and displacement components so memory operations can proceed in parallel with other computation.
• Address space — A namespace defining a set or range of discrete addresses and the entities or storage locations each address can identify under a qualification scheme.
• Analysis of parallel algorithms — The resource analysis of algorithms with cooperating concurrent operations, tracking total work, critical-path span, processor count, time, space, communication, synchronization, and scalability under a declared machine model.
• Cache coherence — The consistency property and protocol discipline that keep multiple cached copies of shared memory observably compatible.
• Cache hierarchy — A layered memory architecture that places progressively larger and slower caches between processors and backing memory to exploit locality at several scales.
• CPU cache — A small fast processor-local memory that retains copies of recently or predictably useful main-memory blocks to reduce average access cost.
• Data buffer — A temporary memory region that decouples a data producer and consumer whose transfer sizes, rates or scheduling do not align.
• Data deduplication — A storage or transfer technique that replaces repeated data regions with references to one retained instance while preserving reconstruction of the original logical data.
• Data dependency — A relation in which one program operation reads or writes a location whose value or ordering is affected by another operation, constraining safe reordering and parallel execution.
• Data scrubbing — A background integrity process that periodically reads stored or memory-resident data, detects latent corruption and reconstructs correct content from checksums, error-correcting codes or redundant copies.
• Firefly (cache coherence protocol) — A three-state write-update cache-coherence protocol that keeps shared cache copies and main memory current on broadcast writes.
• Flat memory model — Expose storage to software as one linearly ordered address space in which an address selects a location without a constitutive segment or bank selector, while allowing paging, protection, caching, or physical translation beneath that programmer-visible contract.
• Instruction pipelining — A processor implementation that divides instruction execution into stages and overlaps different instructions across those stages to increase throughput without requiring each instruction to finish before the next begins.
• Instruction-level parallelism — The degree to which independent machine instructions from one execution stream can overlap or execute simultaneously.
• Load-link/store-conditional — An atomic instruction pair that reads a memory location and commits a later store only if the implementation has observed no conflicting update since the linked load.
• Memory address — Use a fixed-width value within a declared address space to identify an addressable storage unit, with architecture and translation rules determining which physical location a load or store reaches.
• Memory-bound function — A computation whose elapsed time is limited primarily by memory capacity, bandwidth or latency rather than arithmetic throughput.
• MERSI protocol — A five-state cache-coherence protocol extending MESI with a Recent or Read-Only state to optimize shared cache-line ownership and response behavior in PowerPC G4 systems.
• Micro-thread (multi-core) — A software-managed fine-grained threading scheme that overlaps computation with memory or I/O latency on multicore processors.
• Multiple buffering — A producer-consumer technique using two or more buffers so rendering, transfer or processing can proceed concurrently with display or consumption of previously completed data.
• Non-uniform memory access — A shared-memory multiprocessor architecture in which access latency and bandwidth depend on which processor or node physically owns the addressed memory.
• Parallel algorithm — An algorithm organized so multiple operations can execute concurrently on several processing elements while coordinating dependencies and shared data.
• Parallel computing — Execute multiple computations simultaneously across processing elements by decomposing work and coordinating data, communication, synchronization, dependencies, and load to reduce time or increase throughput.
• Parallel RAM — A shared-memory abstract machine for analyzing parallel algorithms by processor count, time and concurrent memory-access rules.
• Scratchpad memory — A small, fast memory explicitly managed by software or a processing unit for temporary data, unlike a hardware-managed cache that automatically mirrors selected main-memory contents.
• Sequential access — An access mode in which elements are reached in a predetermined order and reaching a later element generally requires traversing earlier positions.
• SHA instruction set — Processor instruction extensions that accelerate selected round, schedule and Boolean primitives of SHA-family cryptographic hash functions.
• Shared memory — A memory region or address-space resource that multiple execution agents can access for communication or coordinated computation.
• Single instruction, multiple data — A parallel-computing organization in which many processing lanes perform the same instruction simultaneously on different data elements.
• Virtual address space — The process-visible range of virtual memory addresses that an operating system maps, protects and backs independently of the machine's physical-address layout.
• Virtual memory — Give each process a protected logical address space by translating virtual addresses to physical storage and managing residency, protection, sharing, and replacement independently of the program's apparent contiguous memory.
• Visual Instruction Set — A family of SPARC V9 SIMD instruction-set extensions that perform parallel media, signal and pixel operations in floating-point register storage.