Memory Systems

Jacob, B., Ng, S. W., & Wang, D. T. (2008). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann.

Type

Book

Intellectual base

Review or monograph

Year

2008

Pages cited

10-14

DOI

10.1016/b978-0-12-379751-3.x5001-2

ISBN

9780123797513

DOI registrant

Elsevier

Link

https://doi.org/10.1016/B978-0-12-379751-3.X5001-2

Cited from

psychology

Cited by

3 citations across 3 artifacts.

Each citation links to the sentence it supports in the citing article.

Primes

• Maintenance Rehearsal
  • In hardware memory, dynamic cells leak charge and must be refreshed every few milliseconds or their contents are lost, with refresh circuitry reading and rewriting each row continuously.

    This sourceExplains DRAM operation: capacitor cells leak charge and must be periodically refreshed (read-and-rewrite, e.g. every 64 ms) on a period shorter than the worst-case retention time or data is lost.

Domain-specific

• Memory Rank
  • Other command and address signals are commonly shared across ranks; chip select determines which rank responds.
• Memory refresh
  • Memory refresh is the recurring maintenance operation that activates DRAM rows so their weakening cell charges are sensed and restored before retention loss can corrupt the represented bits.

Verification

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