False sharing

Diagnose performance loss when independent data accessed by different processors occupy one coherence block, so writes trigger invalidation, transfer, and reload traffic as though the data were logically shared.

Version

v2 · 2026-09-19 · History

Domain-specific #

1822

Domain group

Applied Sciences & Engineering

Origin domain

Computer Science & Software Engineering

Subdomain

Cache Coherence Performance Pathologies → Computer Science & Software Engineering

Aliases

Cache-line false sharing, False cache-line sharing

Core Idea

False sharing is a performance pathology in a coherent shared-memory system where different processors or threads access logically independent data objects that reside in the same coherence block, and at least one access stream writes. The coherence mechanism tracks ownership and validity at block granularity, not field granularity, so a write to one object can invalidate or transfer the block containing another processor's object. The resulting communication resembles true sharing even though the program does not exchange the affected logical value.

How would you explain it like I'm…

Two Drawings, One Paper

Two kids are drawing their own pictures, but both pictures are on the same sheet of paper. Only one kid can hold the paper at a time, so they keep passing it back and forth and waiting. They aren't sharing a picture, just a page, but it still slows them down. That's False Sharing in computers.

Same Chunk, Different Data

Computers with several processor cores keep small copies of memory in chunks called cache lines. If two cores work on totally separate pieces of data that happen to sit in the same chunk, and at least one of them is changing its piece, the computer acts as though they're sharing. Each time one core writes, the other core's copy is thrown out, and the chunk bounces back and forth. The program slows down even though the cores aren't really exchanging any information. Spreading the data apart in memory can fix it, though it uses up more space.

Cache-Line Ping-Pong

False Sharing is a slowdown in multi-core computers when threads use separate variables that happen to live in the same cache line, and at least one thread writes. The hardware keeps caches consistent per whole line, not per variable, so a write by one core invalidates the line in another core's cache. If the cores keep writing alternately, the line "ping-pongs" between them, causing stalls and poor scaling. True sharing is different: there, threads really do communicate through the same variable. Two threads that only read don't cause this ping-pong. Fixes like padding or giving each thread its own copy separate the data, but they can waste cache space, so the problem should be confirmed by measurement first.

 

False sharing is a performance pathology in coherent shared-memory systems: threads on different processors access logically independent data that reside in the same coherence block (usually a cache line), and at least one of them writes. Because coherence protocols track ownership and validity per line, a write by core A requests exclusive ownership and invalidates the line in other caches; core B's next access to its own distinct field then refetches or transfers the line. Alternating writes cause cache-line ping-pong, extra coherence traffic, stalls, and poor scaling, mimicking true sharing even though no logical value is exchanged. Read-only access by both sides generally does not trigger this. The root cause is a mismatch among data layout, work partitioning, scheduling, and coherence granularity. Remedies include padding, alignment, per-thread replication, and data reorganization, each potentially enlarging the working set or hurting spatial locality. Since capacity or conflict misses, lock contention, bandwidth saturation, and NUMA effects produce similar slowdowns, diagnosis should rely on performance counters and address traces, interpreted per architecture, rather than assumed line sizes.

Scope of Application

The abstraction is literal wherever practitioners can identify the same constitutive roles, apply the same boundary tests, and obtain the same kind of output. The following habitats are uses of False sharing itself, not metaphors based only on resemblance.

• Shared counters. Separating per-thread updates that would otherwise occupy one line.
• Queues and ring buffers. Keeping independently written producer and consumer indices off a common coherence block.
• Parallel arrays. Reorganizing fields or chunks so ownership follows the access partition.
• Runtime allocators. Aligning thread-local metadata and preventing adjacent allocations from colliding at line granularity.
• Compiler transformations. Grouping data by accessing processor or splitting falsely shared fields.
• Performance analysis. Using scaling curves and cache-to-cache transfer evidence to distinguish the pathology.

Clarity

A clear account of False sharing must preserve the recognition invariant stated in the Core Idea rather than rely on the title alone. Name the architecture, coherence unit, field addresses, access pattern, and thread placement. Demonstrate that contending accesses target different logical objects within the same block. Separate writes from reads and true sharing from false sharing. Use counters or traces appropriate to the processor rather than treating one event name as universal.

Manages Complexity

False sharing manages complexity by replacing a diffuse field of observations or possible operations with a bounded role structure: coherence block supplies a cache line or other protocol unit is the smallest ownership and invalidation granularity.; independent data objects supplies distinct logical variables share physical placement without sharing program meaning.; multiple processors supplies separate cores or participants cache or request the common block.; write stream supplies at least one participant modifies its object and changes coherence ownership.; invalidation or transfer supplies the protocol moves or invalidates the whole block rather than the written field..

Abstract Reasoning

1. Confirm that the workload loses throughput or gains latency as relevant threads spread across cores.
2. Map hot memory accesses to virtual and physical fields with their byte offsets.
3. Group addresses by the actual coherence block size.
4. Identify lines written by one participant and accessed through a different field by another.
5. Inspect cache-to-cache, invalidation, ownership, and stall evidence where the platform exposes it.

Knowledge Transfer

The strict upward abstraction is Interference And Contention. False Sharing instantiates Interference and Contention because independently useful updates are coupled through a shared hardware bottleneck and each participant's progress imposes avoidable service cost on the others. Within cache coherence performance pathologies, the full mechanism transfers literally when the same roles and boundary tests recur. Beyond that domain, only the parent-level skeleton should travel. Reusing the label False sharing after removing its constitutive vocabulary would hide a change of mechanism behind an analogy. The honest transfer rule is therefore two-stage: recognize the domain-specific pattern first, then lift only the parent relation that remains invariant under a substrate change.

Relationships to Other Abstractions

Current abstraction False sharing Domain-specific

Parents (1) — outgoing typed relations

• False sharing is a kind of Interference and Contention Prime

  False Sharing instantiates Interference and Contention because independently useful updates are coupled through a shared hardware bottleneck and each participant's progress imposes avoidable service cost on the others.

Hierarchy paths (3) — routes to 2 parentless roots

• False sharing → is a kind of Interference and Contention → is a kind of Constraint

Show alternative paths (2)

Neighborhood in Abstraction Space

False sharing sits in a sparse region of the domain-specific corpus (92^nd percentile for distinctiveness): few abstractions share its structure, so a faithful description tends to retrieve it precisely.

Family — Digital Circuit & Memory Architecture (12 abstractions)

Nearest neighbors

• Cache coherence — 0.84
• Cache Inclusion Policy — 0.79
• Firefly (cache coherence protocol) — 0.79
• CPU cache — 0.78
• Cache-Only Memory Architecture — 0.77

Computed from structural-signature embeddings · 2026-10-25