Firefly (cache coherence protocol)¶

A three-state write-update cache-coherence protocol that keeps shared cache copies and main memory current on broadcast writes.

Version: v2 · 2026-09-19 · History
Domain-specific #: 4544
Domain group: Applied Sciences & Engineering
Origin domain: Computer Science & Software Engineering
Subdomain: Computer Architecture → Computer Science & Software Engineering

Core Idea¶

Its valid-exclusive, shared and dirty meanings depend on snooping and bus behavior; write update consumes bandwidth differently from invalidate protocols and the name is DEC-specific. Caches snoop bus transactions, broadcast modified words to every shared copy and memory and use a shared-line response to transition blocks among exclusive, shared and sole-dirty states. The abstraction is therefore identified by a declared carrier, a transformation or constraint over that carrier, and an invariant that tells an analyst whether the named structure is genuinely present.

How would you explain it like I'm…

Shout the New Word

Imagine a few friends who each keep their own copy of the same notebook page. They all sit around one table where everyone can hear. When one friend changes a word, they call out the new word, so everyone with a copy, and the main notebook, writes it down too. That way all the copies stay the same.

Share-the-Update Cache Rules

A computer with several processors gives each one a small fast memory called a cache, which holds copies of data from the main memory. The Firefly protocol keeps those copies matching. Every cache listens to a shared 'bus' where messages travel. When a processor writes to data that other caches also hold, it sends the new value out so every copy and the main memory get updated, instead of telling the others to throw their copies away. A 'shared' signal on the bus tells a cache whether anyone else has a copy, so it knows whether it owns the data alone or shares it.

Snooping Write-Update Protocol

Firefly is a cache coherence protocol, a set of rules that keeps the private caches of multiple processors consistent with each other and with main memory. It is a snooping protocol: every cache watches the transactions on a shared bus. It is also a write-update protocol. When a block is shared, a write broadcasts the modified word to all other copies and to memory. An invalidate protocol instead would tell the other copies to discard themselves, so the two approaches use bus bandwidth differently. Each cache block sits in one of three states: valid-exclusive (the only copy, matching memory), shared, or dirty (the only copy, modified). A shared-line response on the bus tells a cache which state to move into. The name refers to a specific DEC design.

The Firefly protocol is a snooping, write-update cache coherence scheme associated with DEC's Firefly multiprocessor. Each cache block follows a state machine with three states: valid-exclusive (sole clean copy), shared (possibly multiple clean copies), and dirty (sole modified copy, memory stale). Caches monitor bus transactions. On a read or write miss, other caches holding the block assert a shared line, and that response decides whether the requester enters an exclusive or shared state. A write to a shared block broadcasts the modified word on the bus, updating every other cached copy and main memory, so memory stays fresh for shared data. A write to an exclusive block can proceed locally and move the block to dirty without bus traffic. Compared with invalidate protocols such as MESI-style designs, write update avoids re-fetch misses but spends bandwidth on every shared write. Correct analysis requires stating the full system explicitly: caches and memory, the state machine, read and write events, bus transactions and the shared signal, update destinations, memory freshness, the transition table, and the resulting coherence and bandwidth properties.

Scope of Application¶

Firefly (cache coherence protocol) belongs to computer architecture and is useful where the analyst can specify the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, then evaluate the processors caches and memory, cache-block state machine, read and write events, bus transactions and shared signal, update destinations, memory freshness, transition table and coherence and bandwidth properties are explicit. The scope is broad within that domain but bounded by the need for the processors caches and memory, cache-block state machine, read and write events, bus transactions and shared signal, update destinations, memory freshness, transition table and coherence and bandwidth properties are explicit.

Clarity¶

The abstraction clarifies a crowded vocabulary by making the processors caches and memory, cache-block state machine, read and write events, bus transactions and shared signal, update destinations, memory freshness, transition table and coherence and bandwidth properties are explicit the center of the account. A claim should name the carrier, the governing operation or relation, the applicable assumptions, and the recognition test.

Manages Complexity¶

Without the abstraction, an analyst must reason directly over many local details: the carrier roles, admissibility assumptions, competing conventions, derived invariants, boundary cases, and proof or validation obligations specific to Firefly (cache coherence protocol). Firefly (cache coherence protocol) compresses them into the roles in the structural signature. That compression permits comparison across instances without erasing the variables that determine validity. It also exposes which details may be varied safely and which are constitutive.

Abstract Reasoning¶

Identify the carrier. State what the elements, states, objects, or observations are: the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets. Reject examples whose alleged carrier belongs to a different problem.
Lock the constitutive rule. Express the processors caches and memory, cache-block state machine, read and write events, bus transactions and shared signal, update destinations, memory freshness, transition table and coherence and bandwidth properties are explicit independently of one notation or implementation.

Knowledge Transfer¶

Knowledge transfers strongly among subfields of computer architecture because they reuse the typed computer architecture carrier, including objects, relations, parameters, conventions, evidence, boundaries, and comparison targets, Caches snoop bus transactions, broadcast modified words to every shared copy and memory and use a shared-line response to transition blocks among exclusive, shared and sole-dirty states., and type the carrier, state every parameter and convention in the definition, test that the processors caches and memory, cache-block state machine, read and write events, bus transactions and shared signal, update destinations, memory freshness, transition table and coherence and bandwidth properties are explicit, compare the nearest accepted identity, and report counterexamples, uncertainty, and limiting cases.

Relationships to Other Abstractions¶

Current abstraction Firefly (cache coherence protocol) Domain-specific

Parents (1) — outgoing typed relations

Firefly (cache coherence protocol) is a kind of Synchronization Prime

It remains its own entry because its identity is fixed by the processors caches and memory, cache-block state machine, read and write events, bus transactions and shared signal, update destinations, memory freshness, transition table and coherence and bandwidth properties.

Hierarchy paths (7) — routes to 6 parentless roots

Firefly (cache coherence protocol) → is a kind of Synchronization → is a kind of Coordination → presupposes Concurrency

Show alternative paths (6)

Neighborhood in Abstraction Space¶

Firefly (cache coherence protocol) sits in a crowded region of the domain-specific corpus (16^th percentile for distinctiveness): several abstractions share nearly its structure, so a description that fits it tends to fit its neighbors too.

Family — Memory Architecture & Address Spaces (25 abstractions)

Nearest neighbors

Cache coherence — 0.93
CPU cache — 0.92
Cache hierarchy — 0.92
MERSI protocol — 0.91
Shared memory — 0.90

Computed from structural-signature embeddings · 2026-10-25